Problem with timing SRAM connected to FPGA

[uckingcu]

hi ..i am trying to use SRAM connected to fpga...i tried to do synthesis,but i find that timing is not met on input side of bidirectional data bus. the output side has
good positive slack of 5.53 but input side has negative slack of -2.23. i am trying to synthesize for 125MHZ with 6.5ns output offset and 4.5ns input offset. please help me out

 

[sixdegrees]

Re: SRAM timing

Hi
I built an SRAM controller few days back for the 6264 SRAM but I think the frequency was less. Regarding the slack you mention,I dont exactly understand what you mean, can u send the code so that I can try to see the problem. Also if u use ISE there is an SRAM controller for a ZBT SRAM available at Xilinx site,u can have a look at that also

sixdegrees