Whats wrong with this code?

[sixdegrees]

Can anyone tell me what is wrong with the code below?

module lcd_posedge(lcd_clk_in,clk,rst,lcd_latch);

input lcd_clk_in;
//38 hz
input clk;
//main clk
input rst;
output lcd_latch;

wire lcd_clk_in;
wire clk;
wire rst;
wire lcd_latch;


wire lcd_posedge_latch_S;
wire [1:0] edge0;
reg [1:0] edge1;

always @(negedge rst or negedge clk or negedge lcd_clk_in )
begin
if(rst == 1'b1)
begin
edge1 <= 2'b00;
end
else
begin
edge1 <= {edge1[0] ,lcd_clk_in};
end
end

assign lcd_latch = ((( ~edge1[1] )) & edge1[0] );

endmodule


Xilinx tells me the following
ERROR: Xst:898 - "lcd_posedge.v" line 28: The reset or set test condition for <edge1> is incompatible with the event declaration in the sensitivity list.

Plz suggest

 

[benradu]

I am not very familiar with verilog but you can't use more than a clock for your edge1. So remove negedge from rst and lcd_clk_in in the sensitivity list.

 

[tkbits]

You specify negedge for lcd_clk_in, but you use it as a data bit, and it is not part of an if condition. Delete the lcd_clk_in from the sensitivity list.

It's common to specify two edges. One edge must be tested against 1 or 0, and that test must set values to 1 or 0 without logic. The tested edge becomes your async set or reset.

 

[imon]

it's easier to help you out if you write pseudo-code as well.
well, what the message tells you is that
1. you use negedge in the sensitive list while
2. you use rst == 1'b1 in your condition
most likely, that's not how you do asynchronous reset

 

[bbgil]

i tried your code and got the same message but when i remove the compatibility issue with rst, clk and clk in, it synthesize, though warnings comes out in terms of some reg and wire not being used.

always @( negedge lcd_clk_in )
begin
if(rst == 1'b1)
begin
edge1 <= 2'b00;
end

the problems arises from the sensitivity list conflict between the 2 clk and reset. try resolving the clk issues first. what i suggest is you create a separate clock division module and form a hierarchy module, top. then combine and synthesize.

 

[rsrinivas]

always @(posedge clk or negedge reset)
gives an asynchronus FF but ur code has two clocks which doesn't infer any of the FPGA blocks try removing one clk and u may get it done
pls do let us know the results

regards
srinivas

 

[nand_gates]

Checkout this!!
Hope this works

module lcd_posedge(lcd_clk_in,clk,rst,lcd_latch); 
   input clk; //main clk 
   input rst; 
   
   input lcd_clk_in; //38 hz 
   output      lcd_latch; 
   
   wire        lcd_clk_in; 
   wire        clk; 
   wire        rst; 
   wire        lcd_latch; 

   wire        lcd_posedge_latch_S; 
   wire [1:0]  edge0; 
   reg [1:0]   edge1; 
   
   always @(negedge clk or posedge rst )  begin 
      if (rst) 
        edge1 <= 2'b00; 
      else 
        edge1 <= {edge1[0] ,lcd_clk_in}; 
   end 

   assign lcd_latch =  (~edge1[1]) & edge1[0]; 

endmodule