Cant understand VHDL code,somebody plz convert to Verilog

[sixdegrees]

Hi!

I have a code which is a controller for LCD display provided by my FPGA vendor but its written in VHDL. I have a VHDL to Verilog converter and tried using it,it converted the other two files succesfully but cant convert the top level controller. I was wondering those people who are proficient in both can plz help me convert it to Verilog. I dont understand VHDL at all. I have attached the other two files(Verilog) also alongwith the VHDL file.

 

[bansalr]

Re: Cant understand VHDL code,somebody plz convert to Verilo

what is the deal ? i can do this.

 

[nand_gates]

Re: Cant understand VHDL code,somebody plz convert to Verilo

Here it goes...

module lcd_component8 (
   // Outputs
   lcd_clk_led, lcd_clk_38hz, en_led, en1_led, en2_led, vary, data, rw, rs, 
   en, 
   // Inputs
   clk, rst
   );
    input   clk ;        // 40 Mhz
    input   rst ;      
	output   lcd_clk_led ;
	output   lcd_clk_38hz;
	output   en_led	   ;  
	output   en1_led   ; 
	output   en2_led   ; 
	output [4:0]  vary ; 
    output [7:0]  data ; 
    output   rw        ; 
    output   rs        ; 
    output   en        ; 

   // ***************************************************************************
   // system instruntions for lcd display       rs<//d//->
   parameter [7:0] disp_clear 	= 8'b00000001;  // clear disp
   parameter [7:0] addrs_zero 	= 8'b00000010;  // return display
   // parameter [7:0] mod_set   	= 8'b00000110;	// inc counter , don't shift disp
   parameter [7:0] mod_set   	= 8'b00000111;	// inc counter , don't shift disp
   parameter [7:0] disp_cont 	= 8'b00001111;	//disp on, cur on, no blink
   // parameter [7:0] curser_set   = 8'b00010100;  // shift cursre right 
   parameter [7:0] curser_set 	= 8'b00011100;  // shift display right 
   parameter [7:0] function_set = 8'b00110000;  //one line ,5x7,8 bit	
   parameter [7:0] ddram_addr 	= 8'b10000000; 	// sets ddram address
   parameter [7:0] read_flag 	= 8'bzzzzzzzz; 	// read flag and ddram address
   parameter [7:0] busy_ch 		= 8'bzzzzzzzz; 	// read busy 
   // ***************************************************************************
   
   // data convertor for lcd display
   // parameter [7:0] a = 8'b01000001;
   // parameter [7:0] b = 8'b01000010;
   // parameter [7:0] c = 8'b01000011;
   parameter [7:0] d   = 8'b01000100;
   // parameter [7:0] e = 8'b01000101;
   parameter [7:0] f   = 8'b01000110;
   parameter [7:0] g   = 8'b01000111;
   //parameter [7:0] h = 8'b01001000;
   // parameter [7:0] i = 8'b01001001;
   parameter [7:0] j   = 8'b01001010;
   parameter [7:0] k   = 8'b01001011;
   parameter [7:0] l   = 8'b01001100;
   // parameter [7:0] m = 8'b01001101;
   // parameter [7:0] n = 8'b01001110;
   parameter [7:0] o   = 8'b01001111;
   // parameter [7:0] p = 8'b01010000;
   parameter [7:0] q  = 8'b01010001;
   // parameter [7:0] r = 8'b01010010;
   // parameter [7:0] s = 8'b01010011;
   // parameter [7:0] t = 8'b01010100; 
   // parameter [7:0] u = 8'b01010101;
   parameter [7:0] v    = 8'b01010110;
   parameter [7:0] w    = 8'b01010111;
   parameter [7:0] x    = 8'b01011000;
   parameter [7:0] y    = 8'b01011001;
   parameter [7:0] z    = 8'b01011010;
   parameter [7:0] zer  = 8'b00110000;	
   parameter [7:0] one  = 8'b00110001;
   parameter [7:0] two  = 8'b00110010;
   parameter [7:0] thr  = 8'b00110011;
   parameter [7:0] fou  = 8'b00110100;
   parameter [7:0] fiv  = 8'b00110101;
   parameter [7:0] six  = 8'b00110110;
   parameter [7:0] sev  = 8'b00110111;
   parameter [7:0] eig  = 8'b00111000;
   parameter [7:0] nin  = 8'b00111001;
   // parameter  [7:0] eq = 8'b00111101;// = eq
   parameter [7:0] un  = 8'b01011111;// _ under
   parameter [7:0] bl  = 8'b00100000;//   blank
   parameter [7:0] s_q = 8'b00100111;// ' single_q
   parameter [7:0] d_q = 8'b00100010;// " double_q
   parameter [7:0] d_b = 8'b00111011;// ; double_b
   parameter [7:0] py  = 8'b00100001;// | pype
   parameter [7:0] pe  = 8'b00100101;// % percent
   parameter [7:0] qu  = 8'b00111111;// ? Ques
   parameter [7:0] fs  = 8'b00101110;// . Fulstop
   parameter [7:0] dp  = 8'b11001110;// || double pype
   parameter [7:0] da  = 8'b00101101;// -  dash
   parameter [7:0] eb  = 8'b00111101;// =  combination of underscore and upperscore
   parameter [7:0] sl  = 8'b00101111;// /  slash
   
   // reg
   reg [4:0]  vary ; 
   reg [20:0]      clk_div_2, clk_div_1;
   wire            clk1;
   wire            clk_div;
   reg             clk_div1;
   reg             addr_clock;
   reg [9:0]       data_s, data_s1 ;
   reg             enb_s;
   reg [4:0]       addrb_s, addr;    
   reg             clkb_s ;
   reg [7:0]       doutb_s ;
   reg [7:0]       lut_data;
   reg             refresh,refresh_d,start;
   wire            refresh_s;
   
   //reg update_d,update_s;
   reg             en1,en2;
   reg [3:0]       count_s ,count;
   reg             sel;
   wire             clk_delay;
   reg [2:0]       cnt;
   reg [7:0]       lcd_data;
   reg             lcd_clk;//152 Hz
   reg             lcd_posedge_s, lcd_posedge_latch; // pose edge of 152 Hz
   
   parameter       wait_state1  = 0;
   parameter       func_set0    = 1;
   parameter       func_set0_t  = 2;
   parameter       func_set0_t1 = 3;
   parameter       func_set0_t2 = 4;
   parameter       func_set1    = 5;
   parameter       func_set1_t  = 6;
   parameter       func_set2    = 7;
   parameter       func_set2_t  = 8;
   parameter       func_set3    = 9;
   parameter       func_set3_t  = 10;
   parameter       disp_ctrl    = 11;
   parameter       disp_ctrl_t  = 12;
   parameter       clear_disp   = 13;
   parameter       clear_disp_t = 14;
   parameter       mode_set     = 15;
   parameter       mode_set_t   = 16;
   parameter       cur_set      = 17;
   parameter       cur_set_t    = 18;
   parameter       ddram_add    = 19;
   parameter       ddram_add_t  = 20;
   reg [4:0]       ps , ns; 
   
   parameter       wait_state2 = 0;
   parameter       wait_state3 = 1;
   parameter       b           = 2;
   parameter       i           = 3;
   parameter       t1          = 4;
   parameter       m           = 5;
   parameter       a           = 6;
   parameter       p1          = 7;
   parameter       p2          = 8;
   parameter       e           = 9;
   parameter       r           = 10;
   parameter       i1          = 11;
   parameter       n1          = 12;
   parameter       t3          = 13;
   parameter       e1          = 14;
   parameter       o3          = 15;
   parameter       g1          = 16;
   parameter       r1          = 17;
   parameter       a1          = 18;
   parameter       next_line   = 19;
   parameter       t4          = 20;
   parameter       i2          = 21;
   parameter       o1          = 22;
   parameter       n           = 23;
   parameter       t5          = 24;
   parameter       e4          = 25;
   parameter       c2          = 26;
   parameter       h2          = 27;
   parameter       n2          = 28;
   parameter       o2          = 29;
   parameter       l0          = 30;
   parameter       g2          = 31;
   parameter       y2          = 32;
   parameter       p3          = 33;
   parameter       v1          = 34;
   parameter       t6          = 35; 
   
   reg [5:0]       ps1,ns1;

   
   assign data = data_s[7:0] | data_s1[7:0];
   assign rs   = data_s[9] | data_s1[9];
   assign rw   = data_s[8] | data_s1[8];
   assign en      = en1 | en2;
   assign en_led  = en1 | en2;
   assign en1_led = en1;
   assign en2_led = en2;

   assign lcd_clk_led = lcd_posedge_s;
   assign lcd_clk_38hz = lcd_clk;
   assign clk1 = clk_div_1[1]; //(4); //divide by 16 clk = 10m MHz
   assign clk_div = clk_div_2[16];	// divide by 16384 clk1 = 152.587890625 Hz			
   assign clk_delay = clk_div_2[20];
   assign refresh_s = refresh & ~refresh_d;	  	   
   
   //process to divide 40m clk to 4m
   always @(posedge clk or posedge rst) begin 
	  if (rst)
		clk_div_1 <= 0;
	  else
		clk_div_1 <= clk_div_1 + 1;
   end
   
   
   
   //process to divide 4m clk to 244hz
   always @(posedge clk1 or posedge rst) begin 
	  if ( rst ) 
		clk_div_2 <= 0;
	  else
		clk_div_2 <= clk_div_2 + 1;
   end

   //***********************************
   always @(posedge clk or posedge rst) begin
      if (rst)
	    ps <= func_set0;
	  else if (lcd_posedge_s)
	      ps <= ns;
   end


   //next state decoder
   always @(/*AS*/ps) begin
	  case (ps)
     	func_set0    : ns = func_set0_t;
		func_set0_t  : ns = func_set0_t1;
		func_set0_t1 : ns = func_set0_t2;
		func_set0_t2 : ns = func_set1;
		func_set1    : ns = func_set1_t;
		func_set1_t  : ns = func_set2;
      	func_set2    : ns = func_set2_t;
		func_set2_t  : ns = func_set3;
		func_set3    : ns = func_set3_t;
		func_set3_t  : ns = disp_ctrl;
		disp_ctrl    : ns = disp_ctrl_t;
		disp_ctrl_t  : ns = cur_set;	
	    cur_set      : ns = cur_set_t;
		cur_set_t    : ns = mode_set;
		mode_set     : ns = mode_set_t;
		mode_set_t   : ns = ddram_add;
        ddram_add    : ns = ddram_add_t;
		ddram_add_t  : ns = clear_disp;	
		clear_disp   : ns = clear_disp_t;
		clear_disp_t : ns = wait_state1;
		wait_state1  : ns = wait_state1;
		default      : ns = func_set0;
      endcase // case(ps)
   end
   

   //process output decoder
   always @(/*AS*/ps) begin
	  case (ps)
     	func_set0 : begin 
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000110000;
   		   vary = 5'b00001;
        end
     	func_set0_t : begin 
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000110000;
     	   vary = 5'b00010;
        end
     	func_set0_t1 : begin 
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000110000;
     	   vary = 5'b00010;
        end
     	func_set0_t2 : begin 
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000110000;
     	   vary = 5'b00010;
        end
	    func_set1 : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000110000;
		   vary = 5'b00011;
        end
	    func_set1_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000110000;
		   vary = 5'b00100;
        end
      	func_set2 : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
	       data_s = 10'b0000110000;
		   vary = 5'b00101;
        end
      	func_set2_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
	       data_s = 10'b0000110000;			 
		   vary = 5'b00110;
        end
	    func_set3 : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000111000;
		   vary = 5'b00111;
        end
	    func_set3_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000111000;
		   vary = 5'b01000;
        end
		disp_ctrl : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000001110;
		   vary = 5'b01001;
        end
		disp_ctrl_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000001110;
		   vary = 5'b01010;
        end
	    cur_set  : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
    	   data_s = 10'b0000011100;
		   vary = 5'b01011;
        end
	    cur_set_t  : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
    	   data_s = 10'b0000011100;
		   vary = 5'b01100;
        end
		mode_set : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000000110 ;
		   vary = 5'b01101;
        end
		mode_set_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000000110 ;
		   vary = 5'b01110;
        end
        ddram_add : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0010000000;	
		   vary = 5'b01111;
        end
        ddram_add_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0010000000;	
		   vary = 5'b10000;
        end
		clear_disp : begin
		   refresh = 1'b0; 
		   en1 = 1'b1;
		   data_s = 10'b0000000001;
		   vary = 5'b10001;
        end
		clear_disp_t : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000000001;
		   vary = 5'b10010;
        end
		wait_state1 : begin		
		   refresh = 1'b1;
		   en1 = 1'b0;	 						
		   data_s = 10'b0000000000;
		   vary = 5'b10011;
        end
		default : begin
		   refresh = 1'b0; 
		   en1 = 1'b0;
		   data_s = 10'b0000000000;
           vary = 5'b00000;
        end
	 endcase
   end // always @ (...
   

   // to sense refresh=1'b1
   always @(posedge clk or posedge rst) begin
      if (rst == 1'b1)
	     refresh_d <= 1'b0;
	  else if (lcd_posedge_s == 1'b1)
	    refresh_d <= refresh;
   end



   //state2
   always @(posedge clk or posedge rst) begin
      if (rst == 1'b1)
	    ps1 <= wait_state2;
      else if(lcd_posedge_s == 1'b1)
		ps1 <= ns1;
   end 


   always @(/*AS*/ps1 or refresh_s)	begin
      case (ps1)
	    wait_state2 : 
          if (refresh_s == 1'b1)
		    ns1 = b;
	      else
		    ns1 = wait_state2;
	    b  : ns1 = i;
        i  : ns1 = t1;
	    t1 : ns1 = m;
	    m  : ns1 = a;
	    a  : ns1 = p1;
	    p1 : ns1 = p2;
	    p2 : ns1 = e;
	    e  : ns1 = b;		  		  		   
	    default : ns1 = wait_state2 ;
	  endcase // case(ps1)
   end
   
   //output decoder
   always @(/*AS*/ps1) begin
      case (ps1)
	    wait_state2 : begin
		   data_s1 = 10'b0000000000;
           en2 = 1'b0;
        end
	    b : begin
		   data_s1 = 10'b1001000010;//B   
		   en2 = 1'b1;
        end
        i : begin
		   data_s1 = 10'b1001000010;//B
		   en2 = 1'b0;
        end
	    t1 : begin
		   data_s1 = 10'b1001001001;//i	
		   en2 = 1'b1;
        end
	    m : begin
		   data_s1 = 10'b1001001001;//i
		   en2 = 1'b0;
        end
	    a : begin
		   data_s1 = 10'b1001010100;//t
		   en2 = 1'b1;
        end
	    p1 : begin
		   data_s1 = 10'b1001010100;//t
		   en2 = 1'b0;
        end
	    p2 : begin
		   data_s1 = 10'b0000000010;//return home
		   en2 = 1'b1;
        end
	    e : begin
		   data_s1 = 10'b0000000010;//return home
		   en2 = 1'b0;
        end
	    
	    default : begin
		   data_s1 = 10'b0000000000;
		   en2 = 1'b0;
		   start = 1'b0;
		   sel = 1'b0;
        end
      endcase // case(ps1)
   end // always @ (...

   lcd_clk_gen Inst_lcd_clk_gen(
                                // Outputs
                                .lcd_clk(lcd_clk),
                                // Inputs
                                .rst    (rst),
                                .clk    (clk));
   lcd_posedge Inst_lcd_posedge(
                                // Outputs
                                .lcd_latch(lcd_posedge_s),
                                // Inputs
                                .lcd_clk_in(lcd_clk),
                                .clk    (clk),
                                .rst    (rst));
   
endmodule // lcd_component8

I have to change this also....

module lcd_clk_gen(rst, clk, lcd_clk);
   input rst;
   input clk;
   output lcd_clk;
   
   wire   rst;
   wire   clk;
   wire   lcd_clk;
   reg [17:0] Div;
   reg        lcd_clk_s;
   
   //---------lcd CLOCK GENERATION(152 HZ)--------------------------------
   //32M
   always @(posedge clk or posedge rst) begin
      if (rst == 1'b1) begin
         Div <= {18{1'b0}};
      end else begin
         if (Div == 18'b110011011001011110)
           Div <= {18{1'b0}};
         else
           Div <= Div + 1;
      end
   end
   
  //50 % duty cycle--
  always @(posedge clk or posedge rst) begin
     if (rst == 1'b1) begin
        lcd_clk_s <= 1'b 0;
     end else begin
        if (Div > 17'b 11001101100101111)
          lcd_clk_s <= 1'b1;
        else 
          lcd_clk_s <= 1'b0;
     end
  end
  assign lcd_clk = lcd_clk_s;
endmodule

 

[sixdegrees]

Re: Cant understand VHDL code,somebody plz convert to Verilo

Thanx a lot nand_gates....I really need to learn VHDL also I think