Multi cycle instructions in a RISC CPU!!

[sixdegrees]

multicycling instructions

Hello,
I am designing a multicycle RISC CPU which has lots of instructions and various functional units. Now these instructions take variable number of clock cycles and I am required to build the controller FSM for these. I have completed all the ALU functions like fixed point operations,floating point operations,shifter,multiplier etc and I also have the 10 port register file up and ready.But I am required to code the Controller state machine and am struck. From the various examples I got from Opencores etc, all use a simple 1 cycle simplistic alu which returns data on the next cycle but nowhere I can find any info about multicycle controller. I am using Verilog and dont understand VHDL so all you geniuses plz suggest something in Verilog on how to go about it.

I have another big problem,I am required to read my instructions and data from external SRAM chips and have a 40 bit data and 48 program memory bus,so in case I want to connect my FPGA to external RAM chips I will have to use 8 8KSRAM chips which have a 8 bit data bus which sounds really clumsy and unscientific. Can some1 suggest anything?

Added after 3 hours 2 minutes:

Seems like nobody has worked with multi cycle CPU implementations!!

Guess I will have to search somewhere else....I tried reading some organisation books like Patterson and Hennesy but couldnt think of a way to actually map it down to Verilog

 

[Iouri]

intitle:risc cpu

Not sure, It looks like you are making DSP not just a simple RISC

Then why do you need to read 40 bits of data from SRAm?? Can you use instruction pipeline and parser for it...

regarding state machine design search this forum there are few good arcticles was posted...

Also if you don't mind can you please post your CPU architicture


Regards,

 

[sixdegrees]

multicycle risc processor

Well as u correctly guessed it I am designing a Analog Devices ADSP 21020 processor IP core. I have a 40 bit data bus which I have to connect to an external memory like SRAM,the SRAM I am using because the controller is easier to manage. :| I have to either use 5 SRAMs for data transfer or use a single SRAM and do some sort of interfacing so that I can read 5 bytes in subsequent cycles.

Architecture I have to follow strictly according to the manual,in case you cant find on the net plz let me knw. And what exactly do u mean by instruction pipeline and parsing...please clarify a bit,I am not very proficient in architectural designs. My ALU part is more or less up and running, I have a fixed point ALU,floating point unit,shifter and multipliers. Also a 10 port register file which was really cumbersome and have to take care of lots of setup and hold violations. Now the main stumbling block is the Controller FSM design, I have seen a couple of standard designs like XSOC,RISC8,OpenRISC etc found on the net,but none of them have multicycle implementations and most of them use on chip block RAM as source of instructions and data.

Also I am a real newbie at designing large systems on my own, so I am finding myself devoid of engineer's toolkit so to say. :idea: Really need some serious help here

 

[Iouri]

risc cycle

OK let start from the begging then there are few book related to the CPU architecture on this forum just try to search for them first. then I personally not agree of creating ALU first then data structure of the CPU, you need to create your data pass first then attach ALU to it, ALU it last thing what you need to worry when creating your own CPU. Also there are some book avaliable in this forum with respect to sintizable arithmetic operation...

Pipelining means when you fetch the data or instruction it is not going to use in execution at the very next cycle it means it goise in to the data pipe and will be use latter it is done to increace operational speed, or for parsing puropses,

Parsing when instruction had been fetch you need to decode the instruction for example fo something like that C = A + B, you need to fees in to the ALU A, B set up operation adding, and pointed to the register C, then execute actual instruction. From the parsing and then put it in tothe instruction pipe line, for example if you have 8 bit instruction when you decode it it it can go up to 50 or 60 bits total

to manage you 40 bit RAM I am not sure what clock frequency you are planning to use and what size do you need, might be internal RAM modules will make you live easy....


Good lack