Test vector optimization--Need Help

[harii74]

Hello ,
Any body working or know , What are the algorithm are currently being used for Test vectors generation and optimiztion. I mean The test vectors are for testing any ALU core or any IP core. Basically i mean core indepandent test vectors generation and optimization.

Please help me. It will be greatfull to you.


K.Hariharan(harii74).

 

[Iouri]

Not sure what are you talken about: Whow test vector generatore suppose to what limits are for the input values and what result expect as an output. Did you see some refrence for it? if yes please post


regards

 

[sixdegrees]

You have said that you want to test any IP core but you have to first specify what fault models are u looking at, there are various types of fault models available and hundreds of test generation algorithms for the particular fault model,

Also if you are venturing into SOC or Mixed Signal circuits then it becomes a little too complicated,otherwise digital circuits testing is more or less saturated with lots of methods,u might want to read about the following terms,

stuck at faults,delay faults, scan chain,bist, jtag

also there are some commercial tools like Tetra Max which incorporate most of the above mentioned fault models,


hope this helps,

sixdegrees