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Recent content by nmurthy

  1. nmurthy

    How to code in VHDL two concurrent processes in a state of a state machine?

    Re: vhdl synthesis Hi go thro the vhdl code it explains well all that you need to ask hope it helped you
  2. nmurthy

    Simple verilog question

    Here a will get the value of 0 As we all know in race between two or more NBA ,last NBA wins for the case mentioned a<=1; a<=0; hope it helped you
  3. nmurthy

    Blocking & Non- Blocking

    This is wrt Modelsim, correct me if i am wrong in first case a will be 1 ---- bcoz in race of NBA ,last NBA wins and in next case a will be 0 ---- bcoz in race of NBA and BA ,last BA wins hope it helped you
  4. nmurthy

    VHDL data types question

    Your syntax works fine .........
  5. nmurthy

    What's the difference between static and dynamic timing analysis?

    Re: timming analysis can anybody just brief me about how to perform DTA and STA?? with tools/software/process involved..
  6. nmurthy

    What is the difference between the testcase and the testbench in HDL?

    Re: interview #2 Test bench basically a mediator between design and verification environment and test cases are a part of verification environment that has test scenarios to test the design Hope these words covered lot in short
  7. nmurthy

    I2C Communication Help

    any of members here try to throw a light on my question below: What is the difference between I2C,SPI,RS232 and UART explain with specific application if any
  8. nmurthy

    Suggest me a good book on Digital Electronics

    fundamentals of digital electronics 1) Digital Design, Third Edition, by M. Morris Mano. Prentice-Hall, Inc 2) Computer system architecture (3rd ed.) by M. Morris Mano Prentice -Hall, Inc 3) Digital Design: Principles and Practices (3rd) by John F. Wakerly are very good to study i think
  9. nmurthy

    Regarding IC Layout Design

    it's good decision .. Go ahead also TIIT is good institute i think when i was refering to web and curriculum etc., make sure you should get more out of it ( course)
  10. nmurthy

    How the hold time violation occurs?

    Re: Hod time violation In simple words, i would say as below: Max frequecny is determined by the critical paths setup time and hold do not play much role in it we know that max freq is T(min) = CLK to Q delay + Critical path propagation delay + Setup-time We know that Setup time - data...
  11. nmurthy

    doubt regarding random no generation in verilog

    hi sudhir check out the following may be you get some idea **broken link removed**
  12. nmurthy

    What's the purpose of DFT (design for test)?

    Re: DFT :design for test then it must be consuming space and logic and speed in the chip right?? ( because it's a part of chip)
  13. nmurthy

    What is the Time Borrowing concept?

    Re: Time Borrowing Hey See the link below for further info on Time borrowing https://www.velocityreviews.com/forums/t23041-time-borrowing-in-synthesis.html hope it helped you alot
  14. nmurthy

    What's the purpose of DFT (design for test)?

    Re: DFT :design for test hi whether this test logic is outside the chip or inside the chip???
  15. nmurthy

    Why do we need to use scripts and which scripting language is more popular?

    Re: SCRIPTS Scripting a very heart of VLSI Industry in Verification and synthesis process for verifying the designs you need to write simulation or regression scripts so that most of the tasks are automated ( mostly used is Perl) also when you work with synthesis,it requires scripting to...

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