VHDL data types question

[alexz]

How can I initialize constants by incrementing method?

Similar to something like this:

constant a : std_logic_vector(22 downto 0) := (others=>'0');
constant b : std_logic_vector(22 downto 0) := a+1;
constant c : std_logic_vector(22 downto 0) := a+2;
constant d : std_logic_vector(22 downto 0) := a+3;

 

[nand_gates]

constant a : std_logic_vector(22 downto 0) := (others=>'0'); 
constant b : std_logic_vector(22 downto 0) := a+1; 
constant c : std_logic_vector(22 downto 0) := a+2; 
constant d : std_logic_vector(22 downto 0) := a+3;

Works!! whats problem with this??

 

[Iouri]

also you can use arrays

 

[amir81]

you should add "signed" or "unsigned" ieee libraray to your vhdl files; ie:

USE IEEE.std_logic_signed.all;
or
USE IEEE.std_logic_unsigned.all;

depending to your need and definition of function "add" in your project.

 

[nmurthy]

Your syntax works fine .........

 

[kr]

What synthetiser are U using?