doubt regarding random no generation in verilog

[sudhirkv]

when i refered to verilog book, i can generate only signed random no. is there any possibilty to generate unsigned random no in verilog.

 

[nmurthy]

hi sudhir

check out the following
may be you get some idea
**broken link removed**

 

[aji_vlsi]

when i refered to verilog book, i can generate only signed random no. is there any possibilty to generate unsigned random no in verilog.

Not really true:

reg [31:0] unsigned a_reg;

initial a_reg = $random;

Should get you that. It might be true that the $random generates signed number (I would doubt it as $random existed prior to V2K days, when the signed extensions to Verilog came mainstream).

But a pure $random is hardly useful, you need "constrained random", SystemVerilog provides all that!

HTH
Ajeetha, CVC
www.noveldv.com