What is the difference between the testcase and the testbench in HDL?

[verilog_always]

what is the difference between the testcases and testbench In the HDL's

 

[aji_vlsi]

Re: interview #2

what is the difference between the testcases and testbench In the HDL's

A testbench is like a platform on which multiple testcases can be run. Think of it like a microcontroller on a board that can run different Assembly programs.

We delve into these (and many other related topics) at a great depth in our Comprehensive Functional Verification course, see: www.noveldv.com. We will have a class in next 2 weeks time in Bangalore, drop an email to cvc.training <> gmail.com if interested

Regards
Ajeetha, CVC
www.noveldv.com

 

[rakesh_aadhimoolam]

Re: interview #2

A TestBench is something which validates the Code written by you.........

While a Testcase is the input you need to drive to your Inputs of Code with the help of Testbench..........

 

[shnain]

Re: interview #2

Hi,

The testbench is the engine that allow generating entry stimuli for the DUT (Design Under Test), The shape, timing & succession of these stimuli is the testcase.

In short for a DUT verification we write one testbench and multiple testcases, each testcase test a particular functionality of the circuit.

Yours,
Said.

 

[nmurthy]

Re: interview #2

Test bench basically a mediator between design and verification environment
and test cases are a part of verification environment that has test scenarios to test the design

Hope these words covered lot in short

 

[cfriend]

interview #2

In my opinion, testbench contains a lot of testcases

 

[dsairajkiran]

Re: interview #2

i agree with above replies