How the hold time violation occurs?

[verilog_always]

Can any body tell me the how the hold time violation occurs,
I can understand ,how the setup violation is occuring but not the hold time,

Thanks in advance

 

[ahmad_abdulghany]

Re: Hod time violation

What do u mean by "how does it occure?" ?
Kindly clarify more..

Best Wishes,
Hope i can be helpful to u..
Ahmad,

 

[vinod_g]

Re: Hod time violation

Actually while calculating the frequncy we mostly see the SET UP time , but we couldnot include the HOLDTIME , IS there is any CASE where the HOLDtime also included to calculate the frequency

 

[nmurthy]

Re: Hod time violation

In simple words, i would say as below:

Max frequecny is determined by the critical paths setup time and hold do not play
much role in it we know that max freq is
T(min) = CLK to Q delay + Critical path propagation delay + Setup-time

We know that
Setup time - data should be availble before clock edge strikes (if data changes in between then data is lost)
Hold time - data should be stable for atleast this much time after the clock edge has struck (data should not change in this window else metastability will arise)

I Hope it helped you.........

 

[cfriend]

Hod time violation

there may be a larger skew on clock tree