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Recent content by giggs11

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    SynopsysDC : Help With This Error

    Hi guys, I'm trying to set some cell from the link libraries I specified, as driving cells of an input port. However when i try to do this, I get this warning: design_analyzer> set_driving_cell -library MTC35100 -lib_cell IBUF "clk" Performing set_driving_cell on port 'clk'. Error: 'MTC35100'...
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    IO Buffers: What Medium & No Slew Rate...?

    Hi guys, I'm trying to construct my IO padframe but I'm not sure of which IO pad to use from the library: (i) Whats the function of Pull-Up and Pull-Down Transistors and their different ohmic readings in IO pads? (ii) Whats the difference between IO pads with NO slew rates and Medium Slew...
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    Why use PrimeTime when DC can do timing analysis..?

    hi guys, Sarath, you said: "Prime Time has some specialzed inbuillt algorithms for Meeting Timing Puposes. The timing which canot be met by DC can be met by the timingspecific engines associated with Prime time and more over PT as become Timing Sign Off by most Fabs." Can PrimeTime be used...
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    Why use PrimeTime when DC can do timing analysis..?

    Hi guys, I'm in a bit of a confusion here. I'm able to perform timing analysis on Synopsys DC but there is PrimeTime which also does STA. How would PrimeTime be more advantageous than DC's timing analysis..? Can someone point out the advantages and uses of Primetime...? Thanks guys.
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    io limited v/s core limited design

    core limited io If the number of IO ports of a design is small, the the padframe would be typically small in area or perimeter. Now, if the design's perimeter was larger than the padframe's perimeter, this would be termed core limited. Core limited IO pads are "fatter" or wider than IO limited...
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    how interconnect length depends on fanout

    forqa wire load hi, i had the same problem some time ago. The wire load model is an estimation of the wire length of the design. As layout has been achieved through P&R at the synthesis stage, the wiring length estimation has to be made. Anyway, the wire load model has to be chosen on the...
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    anyone have experience of building standard cell library

    Floatgrass, Please specify the book's location. Useless just to say that there is a book in the forum and leave hanging like that....:)
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    Does Func.Simulation require test vectors...?

    hi guys, appreciate the help. just one final query....during functional simulation, does VCS operate similar to Formal verification...? Would VCS require test vectors...? because i know that in Formal verification, the functionality is verified through comparison between HDL design and gate...
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    Difference between HDL Simulation % Gate Level Verification?

    timingcheck instance Hi guys, I'd like to know about HDL simulation process. How does it work...? I usually use a FPGA design entry tool like QuartusII for HDL simulation but am also aware of tools like VCS that can do the job. So, my question is....does the HDL simulator map the design to a...
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    Anyone familiar with DW2000...?

    hi, is anyone using DW2000 for layout work....? I need to know about its installation process. thanks.
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    How to do synthesis without some lib?

    You can't do synthesis without the .DB library. This is assuming that you're using Synopsys DC. Your .LIB has to be compiled by Synopsys Library Compiler to .DB format. But interestingly, I know some research that is going to do library-free synthesis. good luck.
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    Help With Synopsys DC Syntax

    hi, I've written my setup file as such: target library {core_cell.db} link_library {* IO_cell.db Wire_load.db} symbol_library {core_cell.sdb IO_cell.sdb} Assuming that the syntax above is right, My questions are: 1) Can two .sdb libraries be declared under symbol library? 2) IO_cell.db...
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    What is the best way to reduce power for low power ASIC?

    Re: LOW POWER ASIC When it is said that power compiler tools like Power Compiler can be used to optimize power dissipation in a design, how is this done by the tool....? Does the tool re-synthesize the logic to produce a more power efficient circuit...for instance like adding gated clockc...
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    Selecting wire_load model in Synopsys DC

    wire load wl10 hi, A wire load model of 10x10 may denote a die size of 1mm x 1mm. But my wire load model is stated as : wire_load("0 to 50"){ .... .... } wire_load("50 to 100"){ .... .... } what does "0 to 50" and "50 to 100" denote in terms of die size...?
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    Fanout_Load value of an input in Synopsys DC

    hi niuniu, you mentioned that drive strength is a parameter. What is the unit for the parameter...? Is it the total capacitance that can be driven by the output...?
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