giggs11
Member level 3
10x10 wire load
hi all,
i'm attempting to run some HDL synthesis on Synopsys DC but am very confused on how to choose the appropriate Wire Load model.
As i understand it, Wire loading models contain all the information required by compiler to estimate interconnect wiring delays.wire load model definition contains: area, resistance,capacitance,slope and fanout. all these attributes are given per unit length wire.
But what is meant by 10x10, 5x5 models....? How do we characterize metal wires and what dimensions do we go by to form wire delay models...? Has the choosing of a model during synthesis got anything to do with die design area...?
If anyone any literature or notes relating to wire load models...please let me know where to obtain online.
Help is much appreciated.
hi all,
i'm attempting to run some HDL synthesis on Synopsys DC but am very confused on how to choose the appropriate Wire Load model.
As i understand it, Wire loading models contain all the information required by compiler to estimate interconnect wiring delays.wire load model definition contains: area, resistance,capacitance,slope and fanout. all these attributes are given per unit length wire.
But what is meant by 10x10, 5x5 models....? How do we characterize metal wires and what dimensions do we go by to form wire delay models...? Has the choosing of a model during synthesis got anything to do with die design area...?
If anyone any literature or notes relating to wire load models...please let me know where to obtain online.
Help is much appreciated.