Difference between HDL Simulation % Gate Level Verification?

[giggs11]

timingcheck instance

Hi guys,

I'd like to know about HDL simulation process. How does it work...? I usually use a FPGA design entry tool like QuartusII for HDL simulation but am also aware of tools like VCS that can do the job.

So, my question is....does the HDL simulator map the design to a certain library before functional simulation...? For instance, in an FPGA based HDL Simulator....does the tool map the design to the FPGA cell library before simulation...? because, if it doesn't map to a cell-library, how is it able to deliver the correct timing dependent functionality sim. results..?

I'm also curious of gate-level simulation. I know that after synthesis using Synopsys DC...we target the design to P&R but is there a way to verify the functionality of the synthesized design before P&R...Is this where VCS comes in and hence the requirement of a VHDL library for the step...?

Thanks.

 

[metalwave]

gate level verification

Most design is synchronous design,so we don't consider timing issue first in function verificaton. If function is OK, we will do timing check. If timing is OK, we can full convinced that the function will work.

 

[andromeda]

difference between verification and simulation

Who said that functional simulation give you any information about timing (this is purpose of STA) - as the name functional said, purpose of it is to verify functionality.
Because of aproximation made in functional simulation, part of functionality could not be verified using this (proper initialization, crossing between asynchronous clock domain, ...), so gate-level simulation and other techniques and tools are used for verification of such things.
But, notice that it is not good idea to use gate-level simulation to verify timing (Static Timing Analysis do that job much better). Still, to improve confidence, it is OK to run few gate-level tests with fully back-anotated timings, if you are not absolutely sure about constraints used in STA.

 

[supercst]

gate-level simulation and verification

1) You must provied you library simulation model, for FPGA, it will come with the implementaion tools such as Quatus and ISE.
2) In the simulation model, there is timing checking statement. Function simulation may not check timing,
but gate-level simulation will check the timing, in FPGA simulation, it must provide SDF files.

 

[tukken]

what is timing verification for and gate

yes, you should use pt for STA, but some typical case for post layout sim may be useful for your convince.

 

[khorram]

Re: Difference between HDL Simulation % Gate Level Verificat

You should separate functional verification and timing analysis. If you want to verify the functionality, you don't need any library. Hence simulator does not need any library to do simulation. But if you want to analysis timing, you should introduce a library. In other words, technology maping should be done.

I'm also curious of gate-level simulation. I know that after synthesis using Synopsys DC...we target the design to P&R but is there a way to verify the functionality of the synthesized design before P&R...Is this where VCS comes in and hence the requirement of a VHDL library for the step...?

Before P&R you'd better to do functional verification, because the most important object of delay computation, i.e. routing, has not been done. After P&R, you should do timing analysis to check the timing.

Regards,
KH

 

[mst]

Re: Difference between HDL Simulation % Gate Level Verificat

i got very good document for timing verification . I will upload soon.

 

[funzero]

Re: Difference between HDL Simulation % Gate Level Verificat

simulation focus on functionality & dynimic property .
gate focus on timing performnace and function .