Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by casey480

  1. C

    Determining filter archtecture from the frequency response

    Is there an easy or straightforward way to analyze a frequency response plot/filter profile of a digital filter and determine it's architecture (number of taps, FIR vs IIR, decimation rate, coefficients, etc) For example, what information do i have about the filter and it's implementation by...
  2. C

    DFT & Synthesis: Scan clock inversion and non-unate warning

    Yes, that is what I do. All registers are posedge, with negedge clocks created before they are used. Also, the test_mode register in question indicates that a key signature has been written. It *cannot* be set or cleared without mantipulating an external pin which will be controlled by the...
  3. C

    DFT & Synthesis: Scan clock inversion and non-unate warning

    All, I am synthesizing a basic design with three clock domains and the occasional negedge flop. To make reordering not an issue for negedge flops, I invert the clock with scan_mode. The scan_mode signal is generated from a flop within the design. The tool reports Warning: A non-unate path...
  4. C

    DSP: cascaded integrated comb filters

    I'm trying to work out the output states for each stage of a CIC, and I'm a bit confused. If an integrator looks like this: **broken link removed** And it's output is described as S1[n] = S1[n-1] + X1[n] If you cascaded two of them, the output of the second stage: S2[n] = S2[n-1] +...
  5. C

    Clock Tree Synthesis (CTS) with Cadence Encounter

    I am attempting to design a clock tree for a design with clock gating. I am having trouble understanding the syntax for the ctcsh. My design gates a clocks for power and functionality. In each case, devices clocked by the gated clock are expected to be synchronous with devices clocked by the...
  6. C

    report_timing through asynch paths: the reset of a flip flop

    For characterization purposes, I'd like to know the timing from pin 'reset_b' of my design, through combo logic, thru the 'RB' pin of a specific flop, thru the 'Q' of that same flop, and then to an arbitrary point on my design. This is not a sequential path, and PrimeTime reports all attempts...
  7. C

    DFT: What is sequential depth?

    Re: seq depth sequential depth is the number of capture cycles executed before unloading your scan chains. so if your sequential depth was one, you would have a pattern sequence as follows: 1) set scan_enable, load scan chain, unset scan_enable 2) execute 1 capture clock 3) set scan_enable...
  8. C

    problems in synthesis with DC

    First, why don't you want your counter optimized? Second, Are you sure the design has been mapped to your library? The first thing DC does is translate the RTL to what are called 'GTECH' generic gates. Then it maps from GTECH to your intended library. Open up the netlist and look around...
  9. C

    constraining a generated clock that is also an output?

    i have a generated clock 'i_clk' which is a divide by two created from a flip flop clocked by 'user_clock' thus, i have the following constraint: create_generated_clock -source [get_pins user/user_clk_mux/O] [get_pins user/i_clk_reg/Q] -name I_CLK -divide_by 2 i_clk is also an output of the...
  10. C

    Constraining a "sticky" register for synthesis

    ah, a clock on the signal rather than the port. makes sense. thanks!
  11. C

    Constraining a "sticky" register for synthesis

    I am using a register in a non-typical fashion. The rising edge of signal 'A' will set this register. It is reset asynchronously by signal 'B'. Signal 'A' is acting like a clock on this register, but not on other logic, so i am hesitant to create a clock on that port. How do i constrain this...
  12. C

    Validation: Creating command structures using System Verilog

    I have a DUT with two interfaces, and similar commands can be executed on each. cmd_int_a would have a different opcode than cmd_int_b, but the same payload and net effect. How can I efficiently abstract this and write a test which can run on either interface? Use a function to translate...
  13. C

    Analog IO VS Digital IO ?

    Also, digital I/O cells may have a Schmidt trigger on them, which would be desctruvtive for an analog signal.
  14. C

    processing .bmp file using verilog testbench

    maybe convert the bmp from a binary to an hexadecimal represented ascii file, and then read it into verilog with $readmemh. Use google to find a utility. The ASCII file may require massaging via a Perl script to get it into a format that verilog can parse.
  15. C

    clk synchronous design methodologies

    Do you mean you want the two clocks to come into phase with one another? Or do you want to synchronously select either clock without glitching? Talk more about your intended result.
See more

Part and Inventory Search

Back
Top