Aimerbhat
Newbie level 5
Hello all,
I am trying to synthesize gate level logic of my behavior level code(verilog) by design compiler . i am using faraday 130nm library. I have a divided clock derived from a 7 bit counter . I made the network as dont touch (counter) so that synthesizer wont try to optimize and modify it . After synthesis i tried to simulate the gate level netlist on modelsim with the source file of the library and .sdf file .
while simulation modelsim is giving error of Module '\**SEQGEN** ' is not defined.
in the synthesized netlist , this cell is used for forming the counter.
1) what i feel is that i should also specify the standard cell to be used to make the counter network.
*but dont know how to specify that --- command in DC - help in this regard
2) Hard code the counter block structurally. This would be a lengthy affair .
i am just check Dynamic time analysis and and there would be other blocks also in the design whos timing are not met ...
what is general procedure to deal with such problems in synthesis .
kindly help ... i am a newbie in this field
regards
Aimer
I am trying to synthesize gate level logic of my behavior level code(verilog) by design compiler . i am using faraday 130nm library. I have a divided clock derived from a 7 bit counter . I made the network as dont touch (counter) so that synthesizer wont try to optimize and modify it . After synthesis i tried to simulate the gate level netlist on modelsim with the source file of the library and .sdf file .
while simulation modelsim is giving error of Module '\**SEQGEN** ' is not defined.
in the synthesized netlist , this cell is used for forming the counter.
1) what i feel is that i should also specify the standard cell to be used to make the counter network.
*but dont know how to specify that --- command in DC - help in this regard
2) Hard code the counter block structurally. This would be a lengthy affair .
i am just check Dynamic time analysis and and there would be other blocks also in the design whos timing are not met ...
what is general procedure to deal with such problems in synthesis .
kindly help ... i am a newbie in this field
regards
Aimer