Constraining a "sticky" register for synthesis

[casey480]

I am using a register in a non-typical fashion. The rising edge of signal 'A' will set this register. It is reset asynchronously by signal 'B'.

Signal 'A' is acting like a clock on this register, but not on other logic, so i am hesitant to create a clock on that port. How do i constrain this register properly?

Thanks.

 

[RBB]

Create a clock for signal A.

 

[cie40]

And make it enabled for this variable like 'clock as data' enabled in synthesis and PNR's variables.

 

[casey480]

ah, a clock on the signal rather than the port. makes sense. thanks!

 

[cie40]

Define a clock on the pin or port driving(generating) the signal A.