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If there is no idle cycle in write, and writes keep happening, and ur read is happening at 1/2 the frequency of write, then ur fifo depth can only be infinite.
To answer ur 2nd question, think of this scenario.
writing into the FIFO is being done with a burst of 8 and reading is done with bursts of 4 with a delay between 2 reads, which is not a multiple of the clock frequency you are using. In such a scenario, synchronous fifo will be used.
i think some good verilog books are available in the forum itself.
i suggest that you use icarus verilog, which is a verilog simulation tool available for free
http://www.icarus.com/eda/verilog/
Hi,
do we have support for E-language in emacs? if so, where can i get the modules to be installed? if not, r there any proprietary constraints which hamper ppl from developing it?
Hi,
can somebody tell me how the event construct (-> ) is used in writing BFM in verilog? When does a BFM start to initate transcations to the DUT? i know that some event is generated at the start and based on this, the txns are started, but, haven't come across a verilog code like that. It'll...
Hi all,
I'm facing a problem w.r.t reset in my design, or rather, the lack of it. some sections of RTL, which are synchronous sequential blocks, don't have any reset at all and solidify reports these as errors.
Although this doesn't affect my design in anyway, since the regression passes with...
STA doubt
PT, as far as i know, can't fix the timing violations. but, hold violations are fixed using buffers in the P&R stage, or by adding an additional flop(making sure functionality is met) in the RTL stage.
For setup violation, either better constraints or methods such as inserting...
I'm curious about the business model of your proposed company.
R u looking to market some product or IP or is it going to be a services model, where you will be bidding for projects?
some of the points which i can think of :
1. NMOS can produce a strong 0, but only weak 1(vice versa for PMOS). CMOS can produce strong 1 and a strong 0,i.e. output swings from rail-to-rail.
2. Static power dissipation in NMOS was a problem, CMOS was preferred to NMOS because of this.
3. has...
Hi,
i've a basic question on logical effort. if we compute the ratio of sum of capacitances of the gate to an ideal gate (inverter), we get the logical effort.
if 2-input NAND gate has 2 NMOS in series, 2 PMOS in parallel, then, shouldn't the total capacitance of gate be 5 ? and the LE should...
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