asicengineer1
Member level 2
Hi,
i've a basic question on logical effort. if we compute the ratio of sum of capacitances of the gate to an ideal gate (inverter), we get the logical effort.
if 2-input NAND gate has 2 NMOS in series, 2 PMOS in parallel, then, shouldn't the total capacitance of gate be 5 ? and the LE should be equal to 5/3, right ? but, i saw its given as 4/3. can anyone explain where i'm going wrong ?
thanks.
i've a basic question on logical effort. if we compute the ratio of sum of capacitances of the gate to an ideal gate (inverter), we get the logical effort.
if 2-input NAND gate has 2 NMOS in series, 2 PMOS in parallel, then, shouldn't the total capacitance of gate be 5 ? and the LE should be equal to 5/3, right ? but, i saw its given as 4/3. can anyone explain where i'm going wrong ?
thanks.