Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why Cout/Cin is electrical effort of inverter stages and not Cout/Cg1.(Note here: Cin= external cap placed at 1st inv's gate; Cg1=cap of 1st inv gate)

Status
Not open for further replies.

rashipatel

Newbie
Joined
Feb 2, 2022
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
8
According to the below derivation:
Electrical effort is shown as CL/Cginv.
Cginv term is coming because of Cdnand term. If we connect an external load Cin to the gate of this nand circuit, it will not be related to Cnand in any manner as according to the information given gamma is technology dependent, so I am assuming its related to the parameters of the gate and would not depend on external loads. Please help me clear the confusion here.

1663180731402.png
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top