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LEC is nothing but Logic Equivalence checking.. LEC can be done with Conformal, Formality, Formal PRo tools..
It is basically checking functionality between RTL and Netlist... and also you can check the functionality between pre-layout netlist and post layout netlist just to make sure that P&R tool didnt goofed up anything...
read design <original netlist > -Verilog -Golden -sensitive
read design <post_layout netlist > -Verilog -Revised -sensitive
# Also read memory .v if u have any
add black box <mem_name> -both
add black box <mem_name> -both
set system mode lec
add compare points -all
compare
You can follow the flow from the userguide of Conformal which is from Cadence..
Hi Pinkesh,
do u mean post-sim can be replaced by LEC ?
there is a opinion that SDF back annotated post-sim can be replaced by LEC
what do u think about it ?
Bset Regards,
Arthur
Post sim cannot be replaced by LEC...Post sim is a dynamic testing which ur functional paths are tested.. LEC just checks the proper values are passing in by comparing RTL with netlist or netlist with netlist...
Post sim with SDF annotation is to check for timing with the functionality...here no delays are considered..
Hi
It may be possible to replace sdf-sims with LEC+STA.
A flow can be
RTL->Netlist
Netlist sim without SDF,
STA with proper rspf(parasiticfile) on Post layout netlist
LEC
for RTL vs Netlist.
If you would like to know how to run LEC: and more abou it http://www.vlsiip.com/formality
Kr,
Avi
Hi Avimit,
I just konw about the traditional ASIC flow,
and could you pls email me some materials about the today's ASIC flow ?
and in case I get some error in each step,what should I do?
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