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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 28,598
    25th March 2007, 08:41 Go to last post
    • Replies: 2
    • Views: 115
    Today, 01:57 Go to last post
  1. UART softcore testbench

    Started by promach, 7th June 2017 14:40
    • Replies: 10
    • Views: 1,483
    Yesterday, 23:49 Go to last post
    • Replies: 0
    • Views: 117
    Yesterday, 18:03 Go to last post
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  2. reactive test benches

    Started by ananthan95, Yesterday 11:07
    • Replies: 2
    • Views: 96
    Yesterday, 15:41 Go to last post
  3. Error in interface connection

    Started by muthu7495, 14th December 2017 06:23
    • Replies: 0
    • Views: 138
    14th December 2017, 06:23 Go to last post
    • Replies: 9
    • Views: 506
    13th December 2017, 18:56 Go to last post
  4. What is the definition of macro in Cadence?

    Started by ttxs, 12th December 2017 01:30
    • Replies: 1
    • Views: 346
    12th December 2017, 17:10 Go to last post
  5. 5-bit Sequential Multiplier Design

    Started by jeremeejoseph, 11th December 2017 06:01
    • Replies: 2
    • Views: 441
    11th December 2017, 15:38 Go to last post
  6. creating an one time delay in vhdl test bench

    Started by ananthan95, 9th December 2017 09:56
    • Replies: 3
    • Views: 283
    9th December 2017, 13:27 Go to last post
  7. Help in Alliance synthesis too (SYF)

    Started by Amr_Rashed, 30th November 2017 11:01
    • Replies: 6
    • Views: 2,355
    9th December 2017, 11:46 Go to last post
  8. about primetime output accuracy(significant digits)

    Started by jmaileh.b, 7th December 2017 08:18
    • Replies: 3
    • Views: 346
    9th December 2017, 10:17 Go to last post
  9. Hierarchical rail IR drop analysis in Encounter/Voltus

    Started by alphus, 7th December 2017 11:00
    • Replies: 0
    • Views: 773
    7th December 2017, 11:00 Go to last post
    • Replies: 17
    • Views: 2,435
    7th December 2017, 07:21 Go to last post
    • Replies: 2
    • Views: 902
    6th December 2017, 19:11 Go to last post
    • Replies: 1
    • Views: 568
    30th November 2017, 07:28 Go to last post
  10. Bitcoin Mining IC's or controller

    Started by gauravkothari23, 29th November 2017 19:22
    • Replies: 0
    • Views: 335
    29th November 2017, 19:22 Go to last post
  11. LTC1326-2.5 Orcad model, Pspice Simulation

    Started by Samk0, 28th November 2017 23:26
    • Replies: 0
    • Views: 591
    28th November 2017, 23:26 Go to last post
  12. What is the ring concept for placement blockage?

    Started by ttxs, 28th November 2017 20:24
    • Replies: 3
    • Views: 458
    28th November 2017, 23:14 Go to last post
  13. [SOLVED] What is better in ECO flow

    Started by ua6bqg, 28th November 2017 11:43
    • Replies: 1
    • Views: 505
    28th November 2017, 19:10 Go to last post
  14. [SOLVED] Save/Restore_session commands in the PT in DMSA multi_scenario mode

    Started by ua6bqg, 27th November 2017 13:47
    • Replies: 1
    • Views: 486
    28th November 2017, 18:41 Go to last post
  15. Ocean script fprintf error

    Started by samiran_dam, 28th November 2017 15:21
    • Replies: 2
    • Views: 430
    28th November 2017, 15:27 Go to last post
  16. [SOLVED] Spectre VerilogA not recognize "assign" command

    Started by gutogw, 27th November 2017 15:19
    • Replies: 2
    • Views: 783
    27th November 2017, 23:14 Go to last post
  17. PCIE Rx/Tx engine VHDL code template

    Started by issofui, 27th November 2017 16:00
    • Replies: 0
    • Views: 525
    27th November 2017, 16:00 Go to last post
  18. What are inverting and non-inverting gates

    Started by Spoorthi_Harithas, 25th November 2017 12:14
    • Replies: 6
    • Views: 1,591
    27th November 2017, 15:33 Go to last post