1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    84,676
Page 1 of 781 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 23418

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 09:41
    • Replies: 0
    • Views: 23,639
    25th March 2007, 09:41 Go to last post
  1. Clock frequency after place and route

    Started by oAwad, 20th February 2017 21:15
    • Replies: 4
    • Views: 251
    Today, 09:49 Go to last post
    • Replies: 2
    • Views: 59
    FvM
    Today, 08:27 Go to last post
  2. Disadvantage of downsizing

    Started by shweta.bphc, Today 01:09
    • Replies: 0
    • Views: 86
    Today, 01:09 Go to last post
    • Replies: 0
    • Views: 130
    25th February 2017, 18:50 Go to last post
  3. How to install tessent tool using linux?

    Started by guru2kiot, 25th February 2017 07:20
    • Replies: 0
    • Views: 154
    25th February 2017, 07:20 Go to last post
  4. setDesignMode command in encounter

    Started by oAwad, 24th February 2017 16:43
    • Replies: 5
    • Views: 134
    24th February 2017, 22:03 Go to last post
  5. Adding a new net in SoC encounter

    Started by oAwad, 18th February 2017 19:20
    • Replies: 3
    • Views: 201
    24th February 2017, 20:38 Go to last post
    • Replies: 7
    • Views: 174
    24th February 2017, 20:32 Go to last post
  6. Voltus CL View generation

    Started by aditya1579, 23rd February 2017 20:03
    • Replies: 0
    • Views: 195
    23rd February 2017, 20:03 Go to last post
  7. RC extraction in SoC encounter

    Started by oAwad, 22nd February 2017 21:59
    • Replies: 4
    • Views: 179
    23rd February 2017, 19:30 Go to last post
  8. Help with nanosim vector input

    Started by mavericknik, 23rd February 2017 18:47
    • Replies: 0
    • Views: 168
    23rd February 2017, 18:47 Go to last post
  9. SPEF file in encounter

    Started by oAwad, 23rd February 2017 13:59
    • Replies: 0
    • Views: 164
    23rd February 2017, 13:59 Go to last post
  10. Minimum gap between wires in layout

    Started by oAwad, 19th February 2017 22:53
    • Replies: 11
    • Views: 287
    23rd February 2017, 04:14 Go to last post
  11. How to locate nodes in SPEF file

    Started by oAwad, 22nd February 2017 21:53
    • Replies: 0
    • Views: 116
    22nd February 2017, 21:53 Go to last post
  12. timing violation netlist simulation

    Started by l.chelini, 22nd February 2017 15:30
    • Replies: 4
    • Views: 213
    22nd February 2017, 19:57 Go to last post
  13. Vhdl Netlists merging

    Started by hanif, 22nd February 2017 10:32
    • Replies: 0
    • Views: 166
    22nd February 2017, 10:32 Go to last post
  14. DRC errors reported by Synopsys Hercules

    Started by bhaismachine, 16th February 2017 01:03
    • Replies: 12
    • Views: 265
    22nd February 2017, 07:22 Go to last post
  15. Negative Latch in Clock Gating

    Started by identical, 19th February 2017 00:14
    • Replies: 2
    • Views: 197
    22nd February 2017, 03:24 Go to last post
    • Replies: 3
    • Views: 160
    21st February 2017, 23:36 Go to last post
  16. Cells that violates max capacitance constraints

    Started by siy010, 20th February 2017 07:10
    • Replies: 7
    • Views: 145
    21st February 2017, 19:03 Go to last post
  17. Comparing read and write pointers in Asynchronous FIFO

    Started by identical, 21st February 2017 17:35
    • Replies: 1
    • Views: 171
    21st February 2017, 19:01 Go to last post
  18. Problem importing GDS file to Virtuoso

    Started by oAwad, 21st February 2017 15:04
    • Replies: 2
    • Views: 197
    21st February 2017, 15:42 Go to last post
    • Replies: 2
    • Views: 164
    21st February 2017, 15:42 Go to last post
  19. how we get fanin through TCL

    Started by sarfaraz.ahmed, 21st February 2017 14:21
    • Replies: 0
    • Views: 164
    21st February 2017, 14:21 Go to last post
  20. synthesis tcl file though rc compiler

    Started by sarfaraz.ahmed, 20th February 2017 15:24
    • Replies: 2
    • Views: 197
    21st February 2017, 06:46 Go to last post
  21. Update the design netlist throught encounter

    Started by oAwad, 20th February 2017 22:00
    • Replies: 0
    • Views: 173
    20th February 2017, 22:00 Go to last post
  22. crosstalk in Cadence Virtuoso

    Started by oAwad, 18th February 2017 22:54
    • Replies: 12
    • Views: 288
    19th February 2017, 20:19 Go to last post
  23. how to use libraries in ncverilog

    Started by sarfaraz.ahmed, 19th February 2017 08:41
    • Replies: 2
    • Views: 206
    19th February 2017, 18:55 Go to last post
  24. Power stripes in layout design

    Started by oAwad, 18th February 2017 19:25
    • Replies: 2
    • Views: 149
    19th February 2017, 18:54 Go to last post
  25. Why does clock latency need to decrease?

    Started by identical, 17th February 2017 22:18
    • Replies: 1
    • Views: 231
    18th February 2017, 17:36 Go to last post

Page 1 of 781 1 2 3 11 51 101 501 ... LastLast