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Threads 1 to 30 of 23362

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 09:41
    • Replies: 0
    • Views: 23,280
    25th March 2007, 09:41 Go to last post
    • Replies: 2
    • Views: 115
    Today, 05:09 Go to last post
    • Replies: 0
    • Views: 68
    Yesterday, 22:58 Go to last post
  1. RedHawk Dynamic Analysis -vectorless

    Started by tarjina, 16th January 2017 12:56
    • Replies: 4
    • Views: 257
    Yesterday, 10:13 Go to last post
    • Replies: 6
    • Views: 311
    18th January 2017, 20:54 Go to last post
  2. [SOLVED] TSMC missing schematics ...

    Started by analogLow, 16th January 2017 16:46
    • Replies: 4
    • Views: 315
    17th January 2017, 16:30 Go to last post
  3. SCL Mohali PDKs with Electric/Symica

    Started by Gopalgenius, 26th August 2016 09:37
    • Replies: 2
    • Views: 177
    17th January 2017, 10:26 Go to last post
  4. VERification of APB protocol

    Started by mansi029, 14th January 2017 14:49
    • Replies: 1
    • Views: 168
    16th January 2017, 10:38 Go to last post
  5. icc read verilog problem

    Started by cyrax747, 14th January 2017 10:11
    • Replies: 1
    • Views: 224
    16th January 2017, 05:26 Go to last post
  6. Cadence Encounter CTS

    Started by preethi19, 7th June 2016 04:09
    • Replies: 10
    • Views: 664
    13th January 2017, 07:19 Go to last post
  7. LVS stamping conflict

    Started by argha07, 11th January 2017 09:57
    • Replies: 1
    • Views: 243
    11th January 2017, 23:38 Go to last post
    • Replies: 2
    • Views: 242
    11th January 2017, 22:35 Go to last post
  8. RE: CTS fanout violations

    Started by kenambo, 10th January 2017 14:46
    • Replies: 1
    • Views: 262
    11th January 2017, 22:14 Go to last post
    • Replies: 1
    • Views: 314
    9th January 2017, 04:24 Go to last post
  9. [moved] How gray coding solve metastabiltiy issues ?

    Started by Ltarek, 8th January 2017 14:31
    • Replies: 3
    • Views: 216
    8th January 2017, 19:18 Go to last post
  10. Reordering algorithm

    Started by pat_chan, 7th January 2017 14:47
    • Replies: 1
    • Views: 239
    7th January 2017, 14:58 Go to last post
  11. Encrypted verilog usage in Xilinx ISE ??

    Started by anilineda, 6th January 2017 13:04
    • Replies: 2
    • Views: 302
    6th January 2017, 14:08 Go to last post
  12. Compile ultra problem in dc shell

    Started by cyrax747, 24th November 2016 05:57
    • Replies: 12
    • Views: 535
    6th January 2017, 01:55 Go to last post
  13. where signal routing is done in physical design flow?

    Started by yuhiub90, 4th January 2017 15:30
    • Replies: 6
    • Views: 289
    5th January 2017, 05:26 Go to last post
  14. look for some reference code for ahb matrix

    Started by wyn2252128, 24th December 2016 10:37
    • Replies: 4
    • Views: 250
    4th January 2017, 11:18 Go to last post
  15. Logical equivalence between verilog and .lib

    Started by reddvoid, 3rd January 2017 12:51
    • Replies: 2
    • Views: 300
    4th January 2017, 08:26 Go to last post
  16. *Negative setup and Hold

    Started by AmarMohan, 28th December 2016 06:47
    • Replies: 1
    • Views: 276
    4th January 2017, 08:21 Go to last post
    • Replies: 1
    • Views: 274
    4th January 2017, 08:03 Go to last post
  17. Break-even point analysis using DC-Topo

    Started by shr_ud, 3rd January 2017 13:23
    • Replies: 0
    • Views: 151
    3rd January 2017, 13:23 Go to last post
    • Replies: 1
    • Views: 287
    3rd January 2017, 02:59 Go to last post
  18. VHDL Simulation warning / Error

    Started by manojrote, 30th December 2016 13:12
    • Replies: 2
    • Views: 339
    2nd January 2017, 09:59 Go to last post
    • Replies: 3
    • Views: 301
    1st January 2017, 05:49 Go to last post
  19. Clock gating cells delays in post-map simulation

    Started by alphus, 13th December 2016 09:22
    • Replies: 3
    • Views: 300
    29th December 2016, 16:05 Go to last post
    • Replies: 2
    • Views: 259
    29th December 2016, 16:02 Go to last post
  20. BCH code (63,56) as expurgated Hamming (63,57) code

    Started by poluekt, 25th July 2016 08:05
    • Replies: 1
    • Views: 341
    29th December 2016, 10:09 Go to last post
  21. Cost of manufacturing discrete power FET

    Started by mrinalmani, 28th December 2016 11:46
    • Replies: 0
    • Views: 251
    28th December 2016, 11:46 Go to last post

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