ss_reddy23
Newbie level 6
The counter does not increment and remains at zero throughout the simulation. Can you someone tell me the mistake in the code.
Functionality expected is to count number of zeros in the given input .
Functionality expected is to count number of zeros in the given input .
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fsmd_0count is port( clk,reset:in std_logic; start:in std_logic; a:in std_logic_vector(7 downto 0); ready:out std_logic; count:out std_logic_vector(3 downto 0) ); end fsmd_0count; architecture rtl_arch of fsmd_0count is type eg_state_type is(idle,add,shift,load); signal current_state,next_state : eg_state_type; signal a_reg,a_next:unsigned(7 downto 0); signal count_reg,count_next:unsigned (3 downto 0); begin process (clk,reset) begin if(reset = '1') then current_state<= idle; a_reg<=(others=>'0'); count_reg<="0000"; elsif(clk'event and clk='1') then current_state <= next_state; a_reg<=a_next; count_reg <= count_next; end if; end process; process(start,current_state,a,a_reg,count_reg,a_next) begin case current_state is when idle => if(start = '1') then if(a="00000000") then count_next<= "1000"; next_state<=idle; ready <='0'; else next_state<=load; ready<='0'; end if; end if; when load => a_next<= unsigned(a); count_next<="0000"; ready<='0'; if(a(0) = '0') then next_state <= add; end if; when add => count_next <= count_reg + "0001" ; next_state <= shift; when shift => a_next<= '0'&a_next(7 downto 1); if(a_next = "00000000") then count_next<="1000"; next_state<= idle; ready<='1'; elsif(a_next(0)='0')then next_state <= add; ready<='0'; elsif(a_next(0) = '1') then next_state <= shift; ready <='0'; end if; end case; end process; --output count <= std_logic_vector(count_next); end rtl_arch;
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