Zero counting circuit

[ss_reddy23]

The counter does not increment and remains at zero throughout the simulation. Can you someone tell me the mistake in the code.

Functionality expected is to count number of zeros in the given input .

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fsmd_0count is
port(
       clk,reset:in std_logic;
         start:in std_logic;
         a:in std_logic_vector(7 downto 0);
         ready:out std_logic;
         count:out std_logic_vector(3 downto 0)
     );
end fsmd_0count;
 
architecture rtl_arch of fsmd_0count is
type eg_state_type is(idle,add,shift,load);
signal current_state,next_state : eg_state_type;
signal a_reg,a_next:unsigned(7 downto 0);
signal count_reg,count_next:unsigned (3 downto 0);
begin
process (clk,reset)
begin
if(reset = '1') then
  current_state<= idle;
  a_reg<=(others=>'0');
  count_reg<="0000";
elsif(clk'event and clk='1') then
  current_state <= next_state;
  a_reg<=a_next;
  count_reg <= count_next;
end if;   
end process;
 
process(start,current_state,a,a_reg,count_reg,a_next)
begin 
      case current_state is 
        
           when idle =>
                 if(start = '1') then 
                    if(a="00000000") then 
                       count_next<= "1000";
                        next_state<=idle;
                        ready <='0';
                     else 
                       next_state<=load;
                        ready<='0';
                    end if;
                end if;    
       
           when load => 
                  a_next<= unsigned(a);
                    count_next<="0000";
                    ready<='0';
                    if(a(0) = '0') then 
                    next_state <= add;
                    end if;
            when add =>
                count_next <= count_reg + "0001" ;
                    next_state <= shift;
                    
            when shift => 
                a_next<= '0'&a_next(7 downto 1);
                    if(a_next = "00000000") then 
                       count_next<="1000";
                       next_state<= idle;
                        ready<='1';
                      
                  elsif(a_next(0)='0')then
                    next_state <= add;
                       ready<='0';
                    elsif(a_next(0) = '1') then 
                      next_state <= shift;
                       ready <='0';    
                    end if;    
                    
          end case;
 end process;
 
--output
 
count <= std_logic_vector(count_next);
                   
 
 
 
 
end rtl_arch;

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[dpaul]

I need to see all the internal signals of the design in waveform, can you post the SS?

Check if your TB is driving the reset signal first HIGH for a few clk cycles and then LOW. I don't see it in the above waveform.

Aghhh.......again this 2 process (current_state,next_state) style of FSM coding! I won't be looking in to it. Please move to 1 process style of FSM coding if possible.

 

[std_match]

I also think you should try "one clocked process only" for writing state machines instead.
The code is now very confusing.
You have latches for several signals in the combinatorial process.
Also, for incrementing an unsigned, you should add 1, not "0001".

 

[ads-ee]

How do you expect help when you don't:

• provide a testbench
• haven't even zoomed the waveforms
• force everyone to play matching games with the signals as the names are cut off.
• cover up the waveform with the pop up for a signal we can see on the waveform.
• You probably ran the simulation without the proper settings to get internal signals to show up in the waveform

You should enable internal signals in the simulation not just ports. Having at the minimum next_state will help tremendously as to what is happening.

From what I can tell from inspecting the code and the simulation waveform you get stuck in the load state and never even go into the state add until around 630ns as the condition a(0) = '0' that transitions the FSM to the add state doesn't occur until a is assigned 0000000 at that point. Besides that you conveniently covered up the waveform with the sim:/ box so we can't see if there was a transition on count at the 4th start pulse (suspect there is one, but we can't see it).

I think you wrote the FSM incorrectly and don't realize (because you never put the next_state signal in the waveform) that the FSM gets stuck in the load state as you didn't define what it should do if the condition is a(0) = '1'.