I need to see all the internal signals of the design in waveform, can you post the SS?
Check if your TB is driving the reset signal first HIGH for a few clk cycles and then LOW. I don't see it in the above waveform.
Aghhh.......again this 2 process (current_state,next_state) style of FSM coding! I won't be looking in to it. Please move to 1 process style of FSM coding if possible.
I also think you should try "one clocked process only" for writing state machines instead.
The code is now very confusing.
You have latches for several signals in the combinatorial process.
Also, for incrementing an unsigned, you should add 1, not "0001".
force everyone to play matching games with the signals as the names are cut off.
cover up the waveform with the pop up for a signal we can see on the waveform.
You probably ran the simulation without the proper settings to get internal signals to show up in the waveform
You should enable internal signals in the simulation not just ports. Having at the minimum next_state will help tremendously as to what is happening.
From what I can tell from inspecting the code and the simulation waveform you get stuck in the load state and never even go into the state add until around 630ns as the condition a(0) = '0' that transitions the FSM to the add state doesn't occur until a is assigned 0000000 at that point. Besides that you conveniently covered up the waveform with the sim:/ box so we can't see if there was a transition on count at the 4th start pulse (suspect there is one, but we can't see it).
I think you wrote the FSM incorrectly and don't realize (because you never put the next_state signal in the waveform) that the FSM gets stuck in the load state as you didn't define what it should do if the condition is a(0) = '1'.