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$ynplify ASIC vs. Design C0mpiler

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joe2moon

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synplify lib2syn

Do anyone here have already benchmark the performance of
$ynplify ASIC ?

I have browsed several places (including $ynplicity's home page), and
still found no official comparision about them.

Although it has cliamed that the run time of $ynplify ASIC is
much faster (x10 or x15) than Design C0mpiler.
And $ynplify ASIC does not make to target the high-performace
market.

But for the application ~500K gate count and ~100MHz,
I am very interesting in the
1) correctness of the synthesied gate-level netlist and
2) the operating frequency which compared to DC.
(Ignore the area here.)
 

edaguy69

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designware fft

$ynplify ASIC is just for FPGA and S*yn*opsys DC is for everything.
It's true that $ynplify ASIC is faster, but we can't compare apple to orange
 

joe2moon

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$ynplicity product(s)

ASIC soultion(s)
1. $ynplify ASIC: logic synthesis
2. Cert!fy: ASIC RTL prototyping
3. F0rtify: power solution

FPGA soultion(s)
1. $ynplify & $ynplify Pr0: FPGA synthesis
2. @mplify: physical synthesis for FPGA
3. Cert!fy SC: FPGA prototyping
4. Ident!fy: RTL debugger
***************************** :eek:
 

buzkiller

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edaguy69 said:
$ynplify ASIC is just for FPGA and S*yn*opsys DC is for everything.
It's true that $ynplify ASIC is faster, but we can't compare apple to orange

$ynplify ASIC, unlike $ynplify Pro, is for ASIC.
 

edaguy69

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Thank for you info, I didn't keep up with the news.
 

Jackal

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Hi!

Ary every body have d/l link for S. ASIC and DC ?

Regard, Jackal.
 

mami_hacky

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I have used both of Synplify ASIC and synopsys Design compiler, I'm mainly working with FPGAs and I do not have a lot of experiance in ASICs.

Any how, Synplify ASIC was very easy to use, I could do a complete synthesis when I opened the soft for the first time. However Design compiler is very very big, it has millions of options and you really need to study some books before using it.

The GUI for Synplify ASIC was much more beautifull than Design Analyzer. ( I used S. ASIC under windows (version 2.1 I think ) and DA under Linux (2002.05) )

Any how, I can say that Synopsys package is really complete. I can say that It is a kind of operating system for itself.

I have not measured the performance of a design under these two tools, but with a simple look, a normal person can say that Synplify has still a very long way to provide some thing like synopsys.

Of course Synplify product's for FPGAs are much more better than Synopsys, But I think that it is not true for ASICs.
 

gordon_wan2k

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GUI is not so GOOD!

GUI is not so GOOD!

I like scripts, it's powerful and can also work with version manager.
I don't require a GUI.

GUI is for someone who don't like scripts. If you cannot write scripts, you cannot work with ASIC sythesis well.
 

joe2moon

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Tapeout with $ynplifyASIC ?

Ask a more practical question:
"Have any one ever taped out by using $ynplify ASIC ?"

Or, have you already planned to tape out your next chip with
the netlist synthesized from $ynplify ASIC ? Will you ?

ps: From SNUG, the ASIC synthesis market no.1 is still
$ynopsys' Design C0mpiler/Physical C0mpiler, and
the far distant no.2 is Magm@....

Thanks in advance ! (for your reply)

/*** Elektroda.pl completes me ! ***/
 

roli

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Magma 2nd place in Synthesis ? - I think you're wrong. Magma is NOT in the Synthesys per-ce' Market.

Magma offers a FULLY integrated tool from ASIC Netlist to GDSII (Synthesis MAY be included - but not a must) - e.g. Floor-Planning, Place&Route, etc.

Magma is a Tool for ASIC Design Centers - who prefer to do the Backend job in-house.
 

azerm

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I think if anyone wants to synthesis any real circuit he can do it with most synthesis tools. I myself have synthesized and also tape out with DC, S.ASIC and even Leo*nardo. (ASIC PROJECTS). All of them works well. But if you want to synthesis a design with more than 200k gates and with newer technologies (like 0.25u and below) there is only five selections:
1- Design Compiler
2- Design Compiler
3- Design Compiler
4- Design Compiler
5- Ambit (Although Design Compiler is better).

Good Luck.
 

papertiger

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Has anyone used more than one tool in one flow?

I am asking this is that we are using SEPKS after DC which will give us some timing improvement due to physical synthesis.
But has anyone compared PC with SEPKS using DC result?

Thanks
 

edaguy69

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roli said:
Magma is a Tool for ASIC Design Centers - who prefer to do the Backend job in-house.
Yes, Magma is a company for Place and Route tools, marketwise it ranks third after Avant! and Cadence, but techologywise it is the best. Wait and see another few years.
 

marsgod

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papertiger said:
Has anyone used more than one tool in one flow?

I am asking this is that we are using SEPKS after DC which will give us some timing improvement due to physical synthesis.
But has anyone compared PC with SEPKS using DC result?

Thanks
I am not sure what the PKS do with placement. For my design,
it create bad placement, but Physical Compiler create better placement
with timing-driven.
Also, the PC cause a lot of time to create and optimize the placement,
and the SOC-Encounter can create a placement very quickly, but the
result is not good.

Then , my flow is :
1, use SOC-Encounter create the floorplan and power plan
2, use PC create the placement , with timing-driven and optimization.
3, use SOC-Encounter create the Clock tree.
4, use PKS do a post CTS optimization
5, use SOC-Encounter do a final power route.
6, use SOC-Encounter's NanoRoute do the detailed route.
7, use PC do a post-route optimization
8, use SOC-Encounter's NanoRoute do a ECO route.
....
...
:)
 

CatKing

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But only a few huge company will adopt both PKS and PhyOpt flow, because they are too expensive, just choose one of them.

There are 3 main RTL to GDS flow:
DC + PhyOpt + Avanti
Ambit + PKS + SE(or Encounter)
Magma
The Synthesis and P&R tools can replaced by other tools, if the physical compile tools has the interface.

One of them is enough for xM gates design, they are too expensive to afford for small companies ($700K per year), Who will really use both PhyOpt and SOC encounter on the same design? That means they will pay $1400K per year only for EDA tools.
 

ljkong

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and many large companys use their-own tools. for example: IBM, Intel, Sun etc.
EDA tools are too expensive.
 

linuxluo

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Hi,
what is PhyOpt ? I use dc and se. is it enough?
Thanks.
 

Ohh

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Hi,

Info about the market share for FPGA synthesis tools [2001: Dataquest]:

- Synplicity 57%
- MentorGraphics 37%
- Synopsys 7%
 

CatKing

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linuxluo said:
Hi,
what is PhyOpt ? I use dc and se. is it enough?
Thanks.
PhyOpt is physical compiler of synopsys, it's unified synthesis and placement tool which can reduce the iterations of the traditional IPO flow.
check the datasheet at:
http://www.synopsys.com/products/unified_synthesis/unified_synthesis.html
But the traditional DC/SE flow still can cover the design below 1M gates and process less than 0.18um well, IPO is time-consume flow which need do multi iterations between the Syn-Place-STA flow to reach the time closure. So you's better have a fast workstation.
 

linuxluo

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Hi, CatKing
I still don't understand IPO. In my view, after p&r , I extracted sdf file and other parasite file and wlm file. When I resynthesis, I use the source file and wlm above to generate optimized netlist , and again sta and p&r until timing closure.
Is it true?
Thanks.
 

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