joe2moon
Full Member level 5
synplify lib2syn
Do anyone here have already benchmark the performance of
$ynplify ASIC ?
I have browsed several places (including $ynplicity's home page), and
still found no official comparision about them.
Although it has cliamed that the run time of $ynplify ASIC is
much faster (x10 or x15) than Design C0mpiler.
And $ynplify ASIC does not make to target the high-performace
market.
But for the application ~500K gate count and ~100MHz,
I am very interesting in the
1) correctness of the synthesied gate-level netlist and
2) the operating frequency which compared to DC.
(Ignore the area here.)
Do anyone here have already benchmark the performance of
$ynplify ASIC ?
I have browsed several places (including $ynplicity's home page), and
still found no official comparision about them.
Although it has cliamed that the run time of $ynplify ASIC is
much faster (x10 or x15) than Design C0mpiler.
And $ynplify ASIC does not make to target the high-performace
market.
But for the application ~500K gate count and ~100MHz,
I am very interesting in the
1) correctness of the synthesied gate-level netlist and
2) the operating frequency which compared to DC.
(Ignore the area here.)