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xilinx timing constrain problem

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jkchen

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i want to perform a serial-in-parallel-out registor.all bufg resource is run out in my spartanii chip.i try two methods:
1.add attribute "uselowskewlines" to the clock net;
2.constrain the clock net and d-flip-flop delay in 20ns;
but it can not solve the problem.is there any other methods i missed?
 

standing_fist

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switch bufg to secondary global buffers

:)
 

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jkchen

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spartanII just got 4 bufg to use.

I have used all for other clocks. no more left.
 

buzkiller

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Give us some more information.
but it can not solve the problem
. What is the problem ? I hope you didn't used a PERIOD constraint for data. :)

regards,
Buzkiller.
 

J

jkchen

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problem solved

reply from xilinx web site.they suggest two methods:
1.use a clock which pass through a bufg(five times than my clock) sample my clock. this methods can make my clock's rising-edge as accuracy as bufg clock.
2.use floorplan to place the nessary logic in a small area.

i used method 1 and plus "uselowskewlines"(i don't know it's useful or not).the problem is solved.

sorry for my poor english.

jkchen
 

wjhzhx

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You test this:
NET xxx MAXSKEW = 0.5 ns;
xxx is your clock which is not drived by bufg.
 

tianxiaduzun

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you should edit the constraint file, and include the constraint file when you synthesize it
 

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