jadedfox
Member level 1
Re: debug...
pls any 1 hlp me catch the bug... in the following code...
I got warning as follows ---
Added after 2 minutes:
why is that counter warning coming? it's not even a port....
pls any 1 hlp me catch the bug... in the following code...
Code:
module adpll(ref_in, en, dco_out);
input ref_in;
input en;
output dco_out;
wire fed_in;
wire up_n;
wire dn_n;
wire rst_n;
wire [7:0] DCO_n;
and an_ck (clk, en, ref_in);
div_10 DV12( .out(fed_in), .in(dco_out), .enable(en1) );
pfd PD1 ( .u1(ref_in), .u2(fed_in), .up(up_n), .dn(dn_n), .rst(rst_n) );
controller CNTRL ( .reset(rst_n), .clk(clk), .up(up_n), .dn(dn_n), .DCO_CONTRL(DCO_n) );
dig_cntrl_osc DCO1 ( .enable(en), .DCO_OUT(dco_out), .DCO_CONTRL(DCO_n) );
endmodule
/////////////////////////////////////////
////////PFD//////////////////////
/////////////////////////////////
module pfd( u1, u2, up, dn, rst);
input u1;
input u2;
output up;
output dn;
output rst;
wire d = 1;
wire rst;
d_ff D1 (.d_in(d), .clk(u1), .reset(rst), .d_out(up));
d_ff D2 (.d_in(d), .clk(u2), .reset(rst), .d_out(dn));
and (rst, up, dn);
endmodule
///////////////////////////////////////////////
module d_ff (d_in, clk, reset, d_out);
input d_in;
input clk;
input reset;
output d_out;
reg d_out;
always @ (posedge reset or posedge clk)
begin
if (reset)
d_out = 1'b0;
else
d_out = d_in;
end
endmodule
///////////////////////////////////////////////////////////////////
////////////////////////CONTROLLER/////////////////////////////
/////////////////////////////////////////////////////////////////
module controller(reset, clk, up, dn, DCO_CONTRL);
input reset, up, dn, clk;
output [7:0] DCO_CONTRL;
reg spd_cnt, freq_acq_mode, ph_acq_mode, step;
reg [7:0] DCO_CONTRL;
wire cond1, cond2, cond3, condp1, condp2;
integer cntf1, cntf2, cntp1, cntp2, s_step;
integer ss;
initial begin
ss <= 64;
end
///////////new one//////////////
//////////Frrequency Acquisition Mode//////////
assign cond1 = freq_acq_mode && step,
cond2 = freq_acq_mode && up,
cond3 = freq_acq_mode && dn,
condp1 = ph_acq_mode && up,
condp2 = ph_acq_mode && dn;
always @ (posedge clk )
begin
if (reset) begin
DCO_CONTRL <= 8'd127;
s_step <= 64;
freq_acq_mode <= 1;
ph_acq_mode <= 0;
cntf1 <= 0;
cntf2 <= 0;
step <= 0;
end
else if (freq_acq_mode) begin
if (s_step == 1) step <= 1;
else step <= 0;
case ({cond1, cond2, cond3})
3'b100:begin
DCO_CONTRL <= DCO_CONTRL;
s_step <= ss;
freq_acq_mode <= 0;
ph_acq_mode <= 1;
cntf1 <= 0;
cntf2 <= 0;
end
3'b010:begin
freq_acq_mode <= 1;
ph_acq_mode <= 0;
cntf2 <= 0;
cntf1 <= cntf1 + 1;
DCO_CONTRL <= DCO_CONTRL + 1;
s_step <= s_step;
if (cntf1 <= 1) begin
s_step <= ss;
s_step <= s_step / 2;
ss <= s_step;
end
end
3'b001:begin
freq_acq_mode <= 1;
ph_acq_mode <= 0;
cntf2 <= cntf2 + 1;
DCO_CONTRL <= DCO_CONTRL - 1;
cntf1 <= 0;
s_step <= s_step;
if (cntf2 <= 1) begin
s_step <= ss;
s_step <= s_step / 2;
ss <= s_step;
end
end
default: begin
DCO_CONTRL <= 0;
s_step <= s_step;
cntf1 <= 0;
cntf2 <= 0;
freq_acq_mode <= 1;
ph_acq_mode <= 0;
end
endcase
end
else if (ph_acq_mode) begin
case ({condp1, condp2})
2'b10:
begin
cntp2 <= 0;
if (cntp1 > 1) begin
cntp1 <= cntp1 + 1;
spd_cnt <= spd_cnt + 1;
s_step <= s_step;
if (spd_cnt == 8) begin
s_step <= s_step * 2;
spd_cnt <= 0;
cntp1 <= 0;
end
end
else begin
cntp2 <= 0;
s_step <= s_step;
if (s_step != 1) s_step <= s_step / 2;
cntp1 <= cntp1 + 1;
spd_cnt <= spd_cnt + 1;
end
end
2'b01:begin
cntp1 <= 0;
if (cntp2 > 1) begin
cntp2 <= cntp2 + 1;
spd_cnt <= spd_cnt + 1;
s_step <= s_step;
if (spd_cnt == 8) begin
s_step <= s_step * 2;
spd_cnt <= 0;
cntp2 <= 0;
end
end
else begin
cntp1 <= 0;
s_step <= s_step;
if (s_step != 1) s_step <= s_step / 2;
cntp2 <= cntp2 + 1;
spd_cnt <= spd_cnt + 1;
end
end
default : begin
cntp1 <= 0;
cntp2 <= 0;
s_step <= 0;
spd_cnt <= 0;
end
endcase
end
end
endmodule
/////////////////////////////////////////////////////
/////////////////////DCO////////////////////////////
///////////////////////////////////////////////////
module dig_cntrl_osc(enable, DCO_CONTRL, DCO_OUT);
input enable;
input [7:0] DCO_CONTRL;
output DCO_OUT;
not invsel0( CONTRL6b, DCO_CONTRL[6] );
not invsel1( CONTRL7b, DCO_CONTRL[7] );
and andsel0( sel0, CONTRL7b, CONTRL6b );
and andsel1( sel1, CONTRL7b, DCO_CONTRL[6] );
and andsel2( sel2, DCO_CONTRL[7], CONTRL6b );
and andsel3( sel3, DCO_CONTRL[7], DCO_CONTRL[6] );
nand nandout( DCO_OUTB, cell1_out, enable );
not INV1( DCO_OUT1B, DCO_OUTB );
bufif1 buf1( cell1_in, DCO_OUT1B, sel3 );
bufif0 buf2( cell1_in, cell2_out, sel3 );
bufif1 buf3( cell2_in, DCO_OUTB, sel2 );
bufif0 buf4( cell2_in, cell3_out, sel2 );
not INV2( DCO_OUT2B, DCO_OUTB );
bufif1 buf5( cell3_in, DCO_OUT2B, sel1 );
bufif0 buf6( cell3_in, cell4_out, sel1 );
bufif1 buf7( cell4_in, DCO_OUTB, sel0 );
not INV3( DCO_OUT, DCO_OUTB );
DCO_CELL cell1( DCO_CONTRL[5:0], cell1_in, cell1_out );
DCO_CELL cell2( DCO_CONTRL[5:0], cell2_in, cell2_out );
DCO_CELL cell3( DCO_CONTRL[5:0], cell3_in, cell3_out );
DCO_CELL cell4( DCO_CONTRL[5:0], cell4_in, cell4_out );
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////
module DCO_CELL( CONT, in, out );
input [5:0] CONT;
input in;
output out;
specify
if(!CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.988;
if(!CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.987;
if(!CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.986;
if(!CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.985;
if(!CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.984;
if(!CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.983;
if(!CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.982;
if(!CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.981;
if(!CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.980;
if(!CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.979;
if(!CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.978;
if(!CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.977;
if(!CONT[5]&!CONT[4]&CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.976;
if(!CONT[5]&!CONT[4]&CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.975;
if(!CONT[5]&!CONT[4]&CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.974;
if(!CONT[5]&!CONT[4]&CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.973;
if(!CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.972;
if(!CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.971;
if(!CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.970;
if(!CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.969;
if(!CONT[5]&CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.968;
if(!CONT[5]&CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.967;
if(!CONT[5]&CONT[4]&!CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.966;
if(!CONT[5]&CONT[4]&!CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.965;
if(!CONT[5]&CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.964;
if(!CONT[5]&CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.963;
if(!CONT[5]&CONT[4]&CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.962;
if(!CONT[5]&CONT[4]&CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.961;
if(!CONT[5]&CONT[4]&CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.960;
if(!CONT[5]&CONT[4]&CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.959;
if(!CONT[5]&CONT[4]&CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.958;
if(!CONT[5]&CONT[4]&CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.957;
if(CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.956;
if(CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.955;
if(CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.954;
if(CONT[5]&!CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.953;
if(CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.952;
if(CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.951;
if(CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.950;
if(CONT[5]&!CONT[4]&!CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.949;
if(CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.948;
if(CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.947;
if(CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.946;
if(CONT[5]&!CONT[4]&CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.945;
if(CONT[5]&!CONT[4]&CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.944;
if(CONT[5]&!CONT[4]&CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.943;
if(CONT[5]&!CONT[4]&CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.942;
if(CONT[5]&!CONT[4]&CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.941;
if(CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.940;
if(CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.939;
if(CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.938;
if(CONT[5]&CONT[4]&!CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.937;
if(CONT[5]&CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.936;
if(CONT[5]&CONT[4]&!CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.935;
if(CONT[5]&CONT[4]&!CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.934;
if(CONT[5]&CONT[4]&!CONT[3]&CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.933;
if(CONT[5]&CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.932;
if(CONT[5]&CONT[4]&CONT[3]&!CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.931;
if(CONT[5]&CONT[4]&CONT[3]&!CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.930;
if(CONT[5]&CONT[4]&CONT[3]&!CONT[2]&CONT[1]&CONT[0]) (in=>out)=0.929;
if(CONT[5]&CONT[4]&CONT[3]&CONT[2]&!CONT[1]&!CONT[0]) (in=>out)=0.928;
if(CONT[5]&CONT[4]&CONT[3]&CONT[2]&!CONT[1]&CONT[0]) (in=>out)=0.927;
if(CONT[5]&CONT[4]&CONT[3]&CONT[2]&CONT[1]&!CONT[0]) (in=>out)=0.926;
if(CONT[5]&CONT[4]&CONT[3]&CONT[2]&CONT[1]&CONT[0] ) (in=>out)=0.925;
endspecify
not m1( out, in );
endmodule
////////////////////////////////////////////////////////
///////////////////////////////////////////////////////
module div_10( enable, in, out );
input enable, in;
output out;
reg out;
reg [3:0] counter;
initial
begin
counter = 4'b0000;
end
always @( negedge enable or posedge in )
begin
if( !enable ) counter <= 4'b0000;
else if( counter == 4'b1010 ) counter <= 4'b0000;
else counter <= counter + 1;
if( !enable ) out <= 1'b0;
else if( counter <= 4'b0100 ) out <= 1'b0;
else out <= 1'b1;
end
endmodule
I got warning as follows ---
Code:
WARNING:Xst:2179 - "adpll.v" line -1: Specify blocks are ignored for synthesis.
WARNING:Xst:646 - Signal <CONT1> is assigned but never used.
WARNING:Xst:2041 - Unit adpll: 1 internal tristate is replaced by logic (pull-up yes): DCO1/cell4_in.
WARNING:Xst:2040 - Unit adpll: 3 multi-source signals are replaced by logic (pull-up yes): DCO1/cell1_in, DCO1/cell2_in, DCO1/cell3_in.
WARNING:Xst:1291 - FF/Latch <PD1/D2/d_out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <PD1/D1/d_out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_0> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_1> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_2> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_3> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <PD1/D2/d_out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <PD1/D1/d_out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_0> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_1> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_2> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_3> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <PD1/D2/d_out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <PD1/D1/d_out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/out> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_0> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_1> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_2> is unconnected in block <adpll>.
WARNING:Xst:1291 - FF/Latch <DV12/counter_3> is unconnected in block <adpll>.
WARNING:Xst:2170 - Unit adpll : the following signal(s) form a combinatorial loop: dco_out.
Added after 2 minutes:
why is that counter warning coming? it's not even a port....