Wild Life
Member level 1
Dear All, I realized an FFT via IP CORE in Xilinx Ise (virtex 5), the problem is that FFT hasn't input enable! So I should have the entire stream of samples to elaborate one sample-per-clock (without missing spaces)! Without other cores when I hadn't samples available I simly put input_enable as '0' waiting for samples' availability. Now, this can't be me made: in N-1 clock cycles i shouls have k-1 samples available... there's a way to have the input-enable function or I'm forced to have the entire frame available?