instantiation error in Xilinx IP CORE

[Andreh12]

Hi everyone.
I have recently been involved in an FPGA project in which I have used an FFT IP core. The attached message appears when I try to instantiate the FFT IP core (in Verilog) and use it in another module. My platform is Xilinx ISE Design Suite version 14.7. It is noteworthy that VHDL instantiation is working properly.

 

[barry]

The message pretty much tells you the problem. it’s looking for a .veo file in a particular place. Is it there? Did the IP generator generate it? (there’s probably a setting somewhere that tells the IP generator that you want a Verilog output. It might be a project setting.

 

[Andreh12]

Thank you for your response.
The directory is the place of storing the project. Yes, IP Generator was used to generate the FFT IP Core.
Since VHDL instantiation works correctly, I thought there is no problem related to the project setting.

 

[barry]

Thank you for your response.
The directory is the place of storing the project. Yes, IP Generator was used to generate the FFT IP Core.
Since VHDL instantiation works correctly, I thought there is no problem related to the project setting.

I don’t remember how ISE 14 works, but maybe there’s a setting that tells ISE it’s a VHDL project or a Verilog project. or, there’s a setting when you generate the IP. Maybe just try regenerating the IP.

I‘m not sure what you mean about the VHDL instantiation working. Do you mean you’ve instantiated the FFT in both VHDL & Verilog modules?

 

[Akanimo]

Seems it was generated in VHDL. There should be a list to select it to be either in VHDL or in Verilog. Maybe VHDL is the default choice and it wasn't changed to Verilog. Check and confirm this.

 

[Andreh12]

Seems it was generated in VHDL. There should be a list to select it to be either in VHDL or in Verilog. Maybe VHDL is the default choice and it wasn't changed to Verilog. Check and confirm this.

I can select the HDL language to be Verilog or VHDL for instantiation. When I choose VHDL for getting an instance, it is okay, but if I choose Verilog for getting the instance, the attached error appears.

 

[barry]

I can select the HDL language to be Verilog or VHDL for instantiation. When I choose VHDL for getting an instance, it is okay, but if I choose Verilog for getting the instance, the attached error appears.

When you select Verilog, do you see the missing file generated? (FFT2.veo). Maybe it's being put in a different directory than is being identified in your error message.

 

[Akanimo]

Are you attempting the core instantiations in both languages in the same project or different projects?