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[SOLVED] Xilinx FFT IP Core - window filtering function is not implemented?

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FlyingDutch

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Hello,

I just has finished study Xilinx documentation for "Fast Fourier Transform v9.1" - see link:

https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_1/pg109-xfft.pdf

and I wasn't able to find information about "window filtering". It seems that such function isn't implemented. I am wondering why?
The same situation with Gowin "FFT" IP core. I thought that such importent function should be implemented in "FFT" IP Core.
I found such article about implementing "window filtering" in FPGA (VHDL):

https://discourse.world/h/2018/10/23/Features-of-window-filtering-on-FPGA

Could somebody give me clues about implementation of "window filtering" in FPGA (especially in Verilog).

Thanks in advance and regards
 

You simply need to apply the window external to the FFT IP.
Hello @barry,

yes now I know - I did a small investigation related to this subject. I tried Xilinx IP Core "FFT" - so far I run generated test-bench. I also checked board with ADS1256 which has arrived to me:

https://pl.aliexpress.com/item/1005...1;62.76;-1;-1@salePrice;PLN;search-mainSearch

I tried this board with Nucleo-F411RE MCU and it works fine with sampling speed 30000sps. Now I would like to connect (write Verilog code) this ADC board to FPGA board with Artix7

Thanks for answer and Regards
 

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