vinod_g
Member level 4
hi all ,
I need some valuable suggestions in one of the my design architecture.
I have one design with clock of 20 Mhz it works on 10 MBps and with clock of 10 Mhz it works with 5 Mbps. These clocks i will generate from PLL. For corresponding bit rate i will generate corresponding clock from PLL. Now my Question is
1. How to make it generic in the sense, depending upon selection bit(configurable from outside) I need to select corresponding frequency from my PLL.
I need to design it and targeting for ALTERA.
I need some valuable suggestions in one of the my design architecture.
I have one design with clock of 20 Mhz it works on 10 MBps and with clock of 10 Mhz it works with 5 Mbps. These clocks i will generate from PLL. For corresponding bit rate i will generate corresponding clock from PLL. Now my Question is
1. How to make it generic in the sense, depending upon selection bit(configurable from outside) I need to select corresponding frequency from my PLL.
I need to design it and targeting for ALTERA.