Hi,
in a dual port memory both sides accesses are asynchronous to each other.
Let´s assume two devices A and B access the same dual port memory.
Even if inside the dual port memory (could be inside an FPGA) there is a common clock to control the access to the RAM cells, one can not be sure if one reads the "old" or the "new" value.
So one solution is to define banks (or blocks). Every block access can be seen from each device as an atomic access.
An example of an application: profibus interface.
(three buffers A, B,C for one direction)
The profibus master (SPS, PLC control) sends data packets to the profibus receiver IC. It stores it´s data in a free block X, during transmission X is marked as "receiving", after receiving the complete packet it is marked as "valid".
(now consider the microcontroller doesn´t read this packet)
If a new packet is received it is stored in a free block Y, during write it is marked as "receiving" afterwards as "valid", and the same time X is marked as free.
(still the microcontroller doesn´t read)
If now a new packet is received it is stored in a free block X, during write it is marked as "receiving"
Now consider the microcontroller wants to read. It looks for the "valid" packet. It is Y. The microcontroller marks it as "reading".
The receive of the packet finishes... X is marked as "valid"
A new packet is received. Data is transferred to free block Z. ... and so on.
At least three blocks are necessary. Each can be marked as "free", "valid", "receiving (data from PLC)", and "reading (data by microcontroller)"
This ensures that all the data within one block is consitent.
The PLC may send 40 packets per second
The microcontroller may asynchronously read with a rate of one packet per second
Klaus