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In analog layout design, is it prohibited to pass power lines trough capacitors and resistors? Why?
When you route over capacitors you are creating a metal 2 metal capacitor. We generally avoid this as much as possible especially when routing sensitive nets. Im not sure why resistors would be a problem, most power lines would be draw using metal 3 or 4 thus keeping away from poly and metal 1.
I think that it is actually due to the EMI and the thermal issues, we should not route VDD lines over resistors and capacitors. Remember that they are very sensitive to temperature and to any other Interference.
In fact, I put the power line through resistors which are bandgap's resistors, and the silicon results are OK. I think that is not a critical issue because you could use top metal as power line.
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