The long edge of the poly gate is much more sensitive to process fluctuations than the short edge of the transistor channel (by costruction).
If you have high CD line variation (the long poly line has irregular edges), the effective length of the transistor is not precise at all.
In order to reduce this error, side dummy MOS are placed to draw a uniform poly pattern and have a good poly printability.
The long edge of the poly gate is much more sensitive to process fluctuations than the short edge of the transistor channel (by costruction).
If you have high CD line variation (the long poly line has irregular edges), the effective length of the transistor is not precise at all.
In order to reduce this error, side dummy MOS are placed to draw a uniform poly pattern and have a good poly printability.
agreed... it used to makesure we can minimize the variation during process... pls take note that we can only minimize it..... the dummy is dropped in order for the operational transistor to see the same invironment at both side source and drain....