macgradywk
Junior Member level 2
Code:
`timescale 1ns/1ns
module test_project1;
reg clk,reset;
reg [7:0] port1;
wire [8:0] port2;
integer file;
initial
file=$fopen("proj.dat","rb");
always@(posedge clk)
$fscanf(file,"%d",port1);
initial
begin
clk = 0;
reset = 0;
reset = #1 1'd1;
reset = #2 1'd0;
end
always
clk = #5 ~clk;
project1 my_project1(port2,port1,clk,reset);
endmodule
simulate it in modelsim
why there is no clock, reset and port2 signal shown,anthing wrong?
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