why no clock and reset signal

[macgradywk]

`timescale 1ns/1ns
module test_project1;
reg clk,reset;
reg [7:0] port1;
wire [8:0] port2;
integer file;
initial   
file=$fopen("proj.dat","rb");
always@(posedge clk)
$fscanf(file,"%d",port1);
  initial
    begin
      clk = 0;
      reset = 0;
      reset = #1 1'd1;
      reset = #2 1'd0;
    end    
  always
    clk = #5 ~clk;
project1 my_project1(port2,port1,clk,reset);
endmodule

simulate it in modelsim
why there is no clock, reset and port2 signal shown,anthing wrong?

 

[mrflibble]

simulate it in modelsim
there is clk and reset, nothing wrong.






Assuming of course you didn't stuff up the my_project1 module and it's instantiation. But no way to check that since you conveniently neglected to post code for that. About the same level of negligence as displayed in describing what the problem is...

 

[macgradywk]

simulate it in modelsim
there is clk and reset, nothing wrong.




Assuming of course you didn't stuff up the my_project1 module and it's instantiation. But no way to check that since you conveniently neglected to post code for that. About the same level of negligence as displayed in describing what the problem is...

I am designing a system that accepts an input data stream x0, x1, x2, . . . at Port1 and produces
a stream of output data points at Port2. Four output points are computed for each set of
four input points. The output stream should look like:
x2, x1 + x2, x0 − x1, x3; x6, x5 + x6, x4 − x5, x7; . . .
Note that each set of 4 outputs are computed in exactly the same manner from a corre-
sponding set of 4 inputs.
All data is 8 bit wide and uses 8-bit 2’s complement arithmetic. On every clock, one data
sample enters and one leaves the system.


Here is the verilog code:

`include "ECE319lib.v"
module project1(port2,port1,clk,reset);
  input[7:0] port1;
  input clk,reset;
  output[8:0] port2;
  reg[8:0] port2;
  reg cl1,cl2,cl3,cl4;
  wire y1,y2,y3,y4,x,y,muxc1,muxc2,cin,cout;
  wire[11:0] B;
  wire[7:0] op1,op2,op3,op4,sum;
  wire[8:0] port3; //since adder exits,we make it one more bit longer
  wire[2:0] muxc3;
  reg[7:0] R1,R2,R3,R4;
  reg[3:0] count;
  always@(posedge clk & cl1)// architecture part begins
  R1<=port1;
  always@(posedge clk & cl2) 
  R2<=port1;
  always@(posedge clk & cl3)
  R3<=port1;
  always@(posedge clk & cl4)
  R4<=port1;// gate clock control data going to each register 
  mux2 #(8) muxA(op1,{R2,R1},muxc1);
  mux2 #(8) muxB(op2,{R3,R2},muxc2);
  xorgate #(8) xor1(op3,x,op1); //+-
  xorgate #(8) xor2(op4,y,op2); //+-
  orgate #(1) my_or(cin,x,y);
  cpa #(8) my_cpa(sum,cout,op3,op4,cin);
  mux8 #(9) muxC(port3,{8'd0,8'd0,8'd0,{cout,sum},R1,R2,R3,R4},muxc3);
  always@(posedge clk)
  port2<=port3;
  decode #(4) my_decoder(B,count);
  always@(posedge clk or posedge reset)// control design
  begin
    if(reset)
      count<=4'd0;
    else
      begin
        if(count==4'd11)
          count<=4'd0;
        else
          count<=count+4'd1;
        end //mod 12 counter
      end
      always@(posedge~clk)//negedge avoid glitch
      begin
        cl1<=y1;
        cl2<=y2;
        cl3<=y3;
        cl4<=y4;
      end
      assign y1=B[0]|B[5]|B[10];
      assign y2=B[1]|B[6]|B[8];
      assign y3=B[2]|B[4]|B[9];
      assign y4=B[3]|B[7]|B[11];
      assign muxc1=B[0]|B[3];
      assign muxc2=B[0]|B[3]|B[8]|B[11];
      assign muxc3={B[0]|B[3]|B[4]|B[7]|B[8]|B[11],B[6]|B[10],B[2]|B[10]};
      assign x=B[8];
      assign y=B[0]|B[4];
    endmodule

with testbench above.

Anything wrong?

 

[mrflibble]

Without even reading any further than this line ...

`include "ECE319lib.v"

... I can predict you neglected to tell us whatever is in ECE319lib.v.

In other words: no way to know if your testbench should work or not since we don't know what it does. That and please use the . Makes it easier to read.

Anyways, currently if I were to run your provided code it would barf due to EDE319lib.v not found, so no way to verify for you what could be going wrong.

Also, could you include a screenshot of your current testbench result and describe what you think is wrong with it.

And I noticed this "always@(posedge~clk)//negedge avoid glitch" ... that always inspires confidence. ;-) So any particular reason you chose to do that?

 

[macgradywk]

Here is the whole thing:
1.Problem:
Design a system that accepts an input data stream x0, x1, x2, . . . at Port1 and produces
a stream of output data points at Port2. Four output points are computed for each set of
four input points. The output stream should look like:
x2, x1 + x2, x0 − x1, x3; x6, x5 + x6, x4 − x5, x7; . . .
Note that each set of 4 outputs are computed in exactly the same manner from a corre-
sponding set of 4 inputs.
All data is 8 bit wide and uses 8-bit 2’s complement arithmetic. On every clock, one data
sample enters and one leaves the system.
2.Verilog code
ECE319lib.v

// Special gates

module andgate(out_op, one_bit_op, in_op);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_op;
  input one_bit_op;
  input [DSIZE-1:0] in_op;
  assign out_op = {DSIZE{one_bit_op}} & in_op;
endmodule

module orgate(out_op, one_bit_op, in_op);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_op;
  input one_bit_op;
  input [DSIZE-1:0] in_op;
  assign out_op = {DSIZE{one_bit_op}} | in_op;
endmodule

module xorgate(out_op, one_bit_op, in_op);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_op;
  input one_bit_op;
  input [DSIZE-1:0] in_op;
  assign out_op = {DSIZE{one_bit_op}} ^ in_op;
endmodule

module xnorgate(out_op, one_bit_op, in_op);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_op;
  input one_bit_op;
  input [DSIZE-1:0] in_op;
  assign out_op = ~({DSIZE{one_bit_op}} ^ in_op);
endmodule

module andsum(out_op, in_op);
  parameter DSIZE=8;
  output out_op;
  input [DSIZE-1:0] in_op;
  wire [DSIZE-1:0] temp;
  assign out_op = temp[DSIZE-1];
  assign temp[0] = in_op[0];
  genvar i;
  generate
  for (i = 1; i < DSIZE; i= i+1)
    begin: gates
      assign temp[i] = temp[i-1] & in_op[i];
    end
  endgenerate
endmodule

module orsum(out_op, in_op);
  parameter DSIZE=8;
  output out_op;
  input [DSIZE-1:0] in_op;
  wire [DSIZE-1:0] temp;
  assign out_op = temp[DSIZE-1];
  assign temp[0] = in_op[0];
  genvar i;
  generate
  for (i = 1; i < DSIZE; i= i+1)
    begin: gates
      assign temp[i] = temp[i-1] | in_op[i];
    end
  endgenerate
endmodule

module evenparity(out_op, in_op);
  parameter DSIZE=8;
  output out_op;
  input [DSIZE-1:0] in_op;
  wire [DSIZE-1:0] temp;
  assign out_op = ~temp[DSIZE-1];
  assign temp[0] = in_op[0];
  genvar i;
  generate
  for (i = 1; i < DSIZE; i= i+1)
    begin: gates
      assign temp[i] = temp[i-1] ^ in_op[i];
    end
  endgenerate
endmodule

module oddparity(out_op, in_op);
  parameter DSIZE=8;
  output out_op;
  input [DSIZE-1:0] in_op;
  wire [DSIZE-1:0] temp;
  assign out_op = temp[DSIZE-1];
  assign temp[0] = in_op[0];
  genvar i;
  generate
  for (i = 1; i < DSIZE; i= i+1)
    begin: gates
      assign temp[i] = temp[i-1] ^ in_op[i];
    end
  endgenerate
endmodule

// Multiplexers and Demultiplexers (Decoders)

module mux2(out_op, in_op, control);
  parameter DSIZE=8;
  input control;
  input [2*DSIZE - 1:0] in_op;
  output [DSIZE-1:0] out_op;
 assign out_op = {DSIZE{(control)}} & in_op[2*DSIZE-1:DSIZE]
                    |{DSIZE{~(control)}} & in_op[DSIZE-1:0];
endmodule

module mux4(out_op, in_op, control);
  parameter DSIZE=8;
  input [1:0] control;
  input [4*DSIZE - 1:0] in_op;
  output [DSIZE-1:0] out_op;
  wire [DSIZE - 1:0] x1, x0;

  mux2 #(DSIZE) mux21(x0, in_op[2*DSIZE-1:0], control[0]);
  mux2 #(DSIZE) mux22(x1, in_op[4*DSIZE-1:2*DSIZE], control[0]);
  mux2 #(DSIZE) mux23(out_op, {x1, x0}, control[1]);
endmodule

module mux8(out_op, in_op, control);
  parameter DSIZE=8;
  input [2:0] control;
  input [8*DSIZE - 1:0] in_op;
  output [DSIZE-1:0] out_op;
  wire [DSIZE - 1:0] x1, x0;

  mux4 #(DSIZE) mux41(x0, in_op[4*DSIZE-1:0], control[1:0]);
  mux4 #(DSIZE) mux42(x1, in_op[8*DSIZE-1:4*DSIZE], control[1:0]);
  mux2 #(DSIZE) mux23(out_op, {x1, x0}, control[2]);
endmodule

module decode(out_op, in_op);
  parameter CSIZE=3;
  input [CSIZE-1:0] in_op;
  output [(1<<CSIZE)-1:0] out_op;
  genvar i;
  generate
  for (i = 0; i < (1<<CSIZE); i= i+1)
    begin: bits
      assign out_op[i] = (in_op == i);
    end
  endgenerate
endmodule

// Tristate

module tristate(out_op, in_op, c);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_op;
  input [DSIZE-1:0] in_op;
  input c;
  genvar i;
  generate
  for (i=0; i < DSIZE; i=i+1)
    begin: buff
      bufif1 u (out_op[i], in_op[i], c);
    end
  endgenerate
endmodule

// Adders

module cpa(out_sum, out_c, in_op1, in_op2, in_c);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_sum;
  output out_c;
  input [DSIZE-1:0] in_op1, in_op2;
  input in_c;
  wire [DSIZE:0] temp_c;
  genvar i;
  assign temp_c[0] = in_c;
  assign out_c = temp_c[DSIZE];
  generate
  for (i=0; i < DSIZE; i=i+1)
    begin: full_add
      assign out_sum[i] = in_op1[i]^in_op2[i]^temp_c[i];
      assign temp_c[i+1]= in_op1[i] & in_op2[i] |
                          (in_op1[i]^in_op2[i]) & temp_c[i];
    end
  endgenerate
endmodule

module csa(out_sum, out_c, in_op1, in_op2, in_c);
  parameter DSIZE=8;
  output [DSIZE-1:0] out_sum, out_c;
  input [DSIZE-1:0] in_op1, in_op2, in_c;
  genvar i;
  generate
  for (i=0; i < DSIZE; i=i+1)
    begin: full_add
      assign out_sum[i] = in_op1[i]^in_op2[i]^in_c[i];
      assign out_c[i]= in_op1[i] & in_op2[i] |
                          (in_op1[i]^in_op2[i]) & in_c[i];
    end
  endgenerate
endmodule

Here is the verilog code:

`include "ECE319lib.v"
module project1(port2,port1,clk,reset);
input[7:0] port1;
input clk,reset;
output[8:0] port2;
reg[8:0] port2;
reg cl1,cl2,cl3,cl4;
wire y1,y2,y3,y4,x,y,muxc1,muxc2,cin,cout;
wire[11:0] B;
wire[7:0] op1,op2,op3,op4,sum;
wire[8:0] port3; //since adder exits,we make it one more bit longer
wire[2:0] muxc3;
reg[7:0] R1,R2,R3,R4;
reg[3:0] count;
always@(posedge clk & cl1)// architecture part begins
R1<=port1;
always@(posedge clk & cl2) 
R2<=port1;
always@(posedge clk & cl3)
R3<=port1;
always@(posedge clk & cl4)
R4<=port1;// gate clock control data going to each register 
mux2 #(8) muxA(op1,{R2,R1},muxc1);
mux2 #(8) muxB(op2,{R3,R2},muxc2);
xorgate #(8) xor1(op3,x,op1); //+-
xorgate #(8) xor2(op4,y,op2); //+-
orgate #(1) my_or(cin,x,y);
cpa #(8) my_cpa(sum,cout,op3,op4,cin);
mux8 #(9) muxC(port3,{8'd0,8'd0,8'd0,{cout,sum},R1,R2,R3,R4} ,muxc3);
always@(posedge clk)
port2<=port3;
decode #(4) my_decoder(B,count);
always@(posedge clk or posedge reset)// control design
begin
if(reset)
count<=4'd0;
else
begin
if(count==4'd11)
count<=4'd0;
else
count<=count+4'd1;
end //mod 12 counter
end
always@(posedge~clk)//negedge avoid glitch
begin
cl1<=y1;
cl2<=y2;
cl3<=y3;
cl4<=y4;
end
assign y1=B[0]|B[5]|B[10];
assign y2=B[1]|B[6]|B[8];
assign y3=B[2]|B[4]|B[9];
assign y4=B[3]|B[7]|B[11];
assign muxc1=B[0]|B[3];
assign muxc2=B[0]|B[3]|B[8]|B[11];
assign muxc3={B[0]|B[3]|B[4]|B[7]|B[8]|B[11],B[6]|B[10],B[2]|B[10]};
assign x=B[8];
assign y=B[0]|B[4];
endmodule

Testbench:

`timescale 1ns/1ns
module test_project1;
reg clk,reset;
reg [7:0] port1;
wire [8:0] port2;
integer file;
initial 
file=$fopen("proj.dat","rb");
always@(posedge clk)
$fscanf(file,"%d",port1);
initial
begin
clk = 0;
reset = 0;
reset = #1 1'd1;
reset = #2 1'd0;
end 
always
clk = #5 ~clk;
project1 my_project1(port2,port1,clk,reset);
endmodule

proj.dat:

12	78	43	66	88	55	56	88	43	23	56	88	76	23	45	67	87	12	32	33	67	98	165	24	124

 

[dftrtl]

Still is this unresolved ?

 

[macgradywk]

I got all the signal, but it does not work correctly,,,I don't know what's wrong

 

[dftrtl]

Provide the waveforms

 

[mrflibble]

I got all the signal, but it does not work correctly,,,I don't know what's wrong

as requested before ...

Also, could you include a screenshot of your current testbench result and describe what you think is wrong with it.

You say " it does not work correctly" ... what in the screenshot of your testbench is not correct and what do you think it should be doing?

 

[mrflibble]

Alright, gave it a quick spin ... and no surprise there, I see a clk and reset just fine in waveforms. So magically the "why no clock and reset signal" is resolved.

Again, what are your testbench results (provide screenshot please), and what's wrong about it in your opinion?