As the snippet of code shown above, I am wondering if it's a good practice to perform logic operation on rst signal. rst signal is a global reset signal. if not, how can i modify the code.
Code Verilog - [expand] 1 2 3 4 5 6 always @(posedge clk) begin counter <= counter + 1; if (rst or reload) begin counter <= load_value; end end
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