gating reset signal

[YuanJin]

As the snippet of code shown above, I am wondering if it's a good practice to perform logic operation on rst signal. rst signal is a global reset signal. if not, how can i modify the code.

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Code Verilog - [expand]
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always @(posedge clk) begin
   counter <= counter + 1;
    if (rst or reload) begin
        counter <= load_value;
    end
end

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[ThisIsNotSam]

this is bad coding style. reset should not be treated as logic, it is a special signal after all. if you follow a traditional template for sequential logic you can avoid this:

always @(posedge clk) begin
  if (reset)
    counter <= load_value;
  else begin
    if (reload)
      counter <= load_value;
    else
      counter <= counter + 1;
  end
end

 

[ads-ee]

this is bad coding style. reset should not be treated as logic, it is a special signal after all. if you follow a traditional template for sequential logic you can avoid this:

always @(posedge clk) begin
  if (reset)
    counter <= load_value;
  else begin
    if (reload)
      counter <= load_value;
    else
      counter <= counter + 1;
  end
end

Unless load_value is a constant, this is only slightly better as reset is still being treated as a logic input (i.e. it is another load enable).

The reset should set the counter to a constant e.g.: (others => '0'), (others => '1'), or some constant value. Using a constant will ensure any dedicated reset resources will be used in the design and not merged into the general purpose logic cells.

 

[FvM]

For most FPGA families, an asynchronous global reset is available without consuming additional logic resources, not a synchronous reset as shown above.

 

[ThisIsNotSam]

Unless load_value is a constant, this is only slightly better as reset is still being treated as a logic input (i.e. it is another load enable).

The reset should set the counter to a constant e.g.: (others => '0'), (others => '1'), or some constant value. Using a constant will ensure any dedicated reset resources will be used in the design and not merged into the general purpose logic cells.

sure, load_value has to be a constant.

 

[YuanJin]

this is bad coding style. reset should not be treated as logic, it is a special signal after all. if you follow a traditional template for sequential logic you can avoid this:

always @(posedge clk) begin
  if (reset)
    counter <= load_value;
  else begin
    if (reload)
      counter <= load_value;
    else
      counter <= counter + 1;
  end
end

Thanks for your answer. Now, I want to consider a similar circuit where I keep reload signal and remove reset signal. If the reload signal is a control signal generated by a FSM. Will it infer a FDRE with reset port connected to 0, while D is connected to a MUX with reload signal acting as a sel signal?

For most FPGA families, an asynchronous global reset is available without consuming additional logic resources, not a synchronous reset as shown above.

Does it mean I don't have to include piece of code dealing with reset signal in a sequential design if the default value of the register is 0?

Unless load_value is a constant, this is only slightly better as reset is still being treated as a logic input (i.e. it is another load enable).

The reset should set the counter to a constant e.g.: (others => '0'), (others => '1'), or some constant value. Using a constant will ensure any dedicated reset resources will be used in the design and not merged into the general purpose logic

Could you please explain why it would be beneficial if the load_value is a const value. How will the xilinx chip be configured in this case?