`include "ECE319lib.v"
module project1(port2,port1,clk,reset);
input[7:0] port1;
input clk,reset;
output[8:0] port2;
reg[8:0] port2;
reg cl1,cl2,cl3,cl4;
wire y1,y2,y3,y4,x,y,muxc1,muxc2,cin,cout;
wire[11:0] B;
wire[7:0] op1,op2,op3,op4,sum;
wire[8:0] port3; //since adder exits,we make it one more bit longer
wire[2:0] muxc3;
reg[7:0] R1,R2,R3,R4;
reg[3:0] count;
always@(posedge clk & cl1)// architecture part begins
R1<=port1;
always@(posedge clk & cl2)
R2<=port1;
always@(posedge clk & cl3)
R3<=port1;
always@(posedge clk & cl4)
R4<=port1;// gate clock control data going to each register
mux2 #(8) muxA(op1,{R2,R1},muxc1);
mux2 #(8) muxB(op2,{R3,R2},muxc2);
xorgate #(8) xor1(op3,x,op1); //+-
xorgate #(8) xor2(op4,y,op2); //+-
orgate #(1) my_or(cin,x,y);
cpa #(8) my_cpa(sum,cout,op3,op4,cin);
mux8 #(9) muxC(port3,{8'd0,8'd0,8'd0,{cout,sum},R1,R2,R3,R4},muxc3);
always@(posedge clk)
port2<=port3;
decode #(4) my_decoder(B,count);
always@(posedge clk or posedge reset)// control design
begin
if(reset)
count<=4'd0;
else
begin
if(count==4'd11)
count<=4'd0;
else
count<=count+4'd1;
end //mod 12 counter
end
always@(posedge~clk)//negedge avoid glitch
begin
cl1<=y1;
cl2<=y2;
cl3<=y3;
cl4<=y4;
end
assign y1=B[0]|B[5]|B[10];
assign y2=B[1]|B[6]|B[8];
assign y3=B[2]|B[4]|B[9];
assign y4=B[3]|B[7]|B[11];
assign muxc1=B[0]|B[3];
assign muxc2=B[0]|B[3]|B[8]|B[11];
assign muxc3={B[0]|B[3]|B[4]|B[7]|B[8]|B[11],B[6]|B[10],B[2]|B[10]};
assign x=B[8];
assign y=B[0]|B[4];
endmodule