Fundamentally we expect setup hold violations on syncronizer
flops. So why to slow down simulation looking for setup hold
violations which are obvious! Other thing is make sure that o/p
of first syncronizing flop should not go 'x' if setup hold violation occures!
Synchronizer flop in the design ensures the latching of any asynchronous signal. It means design by default is robust to deal the timing problems. In gate level Sims any setup/hold violation may propagate the 'x' in this case, which result in unnecessary debug time:|