Why I can't synthesize Verilog code with rising and falling edge?

[hariharan4000]

hi
can any one clear me this problem related wth verilog?
for the folowing stmt

always@(posedge clk or negedge reset)
.
.
.
endmodule
// i am getting the code simulated correctely but NOT synthesisable..
when i change the stmt always@(posedge clk or posedge reset)
it gets synthesised
y i am not getting synthesised i mix rising and falling edge.?
what is the reason?

 

[tarkyss]

Re: a doubt in verilog

which tool?
dc?
I often write code as that,
it is ok

 

[zhangpengyu]

a doubt in verilog

The code of "always@(posedge clk or negedge reset) " is synthesisable.

 

[shreeks]

a doubt in verilog

this looks a tool related problem try with a different tool. the code is very much synthesizable.

 

[nand_gates]

Re: a doubt in verilog

Following DFF code is not synthesizable!!!

module d_ff(clk, reset, d, q);
    input clk, reset, d;
    output q;
    reg q;

always@(posedge clk or negedge reset)
    if (reset)   // this might be the problem!!!
         q <= 1'b0;
     else
          q <= d;

endmodule

This is a big hint!

 

[farmerwang]

Re: a doubt in verilog

You might want to check your target library to see if a async reset (active low) DFF exists. Check your synthesis log file carefully, it will tell you why it's not synthesizable.

 

[semiconductorman]

Re: a doubt in verilog

This is not due to always statement but may be due to one of the statements inside of this block!
check ur code and tell me , have u made any mistake like checking reset == 1 instead of reset==0
In your code it is very much necessary to have active low reset ( u are checking negedge of reset) ... that is asynchronus active low reset. If this is the case then may be u are using a very old tool. which tries to map posedge / negedge to flipflop .. some tools used to do this! . To remove this simply remove the negedge for reset and have something like
always @(posedge clk or reset) .
this wlll solve the problem

 

[skpatel73]

Re: a doubt in verilog

always@(posedge clk or negedge reset)

Shouldn't it be:
always@(posedge clk, negedge reset)

The synthesizer probably thinks you're trying to do a logical OR of two edges.

 

[no_mad]

a doubt in verilog

Hi Hariharan,

There is nothing wrong with the code. It is synthesizable. It just that ur target library did not have an async active low reset DFF.

Check ur target library.

-no_mad

 

[hariharan4000]

Re: a doubt in verilog

hi friends
thanks for ur replies.
i had written as
1)always@(posedge clk or negedge reset)
if(reset) // this was the mistake.
<statements>
when i changed the condition to
2)if(reset ==0)
<statements>
the code gets synthesised.
but is this the problem related with tool??
the same can be tried with the code given for Dff given by Mr.Nand_gates.
the synthesis tool i use is xilinx 6.3.03i and leospec.guys if u r using any latest verson of these tool, plz check it.
regards
hari

 

[anan_tv]

Re: a doubt in verilog

Haii ,

I got the following error in Xilinx ISE 6.1.03i , while i have synthesized the code from Mr.nand gates,

ERROR:Xst:898 - dflp.v line 8: The reset or set test condition for <q> is incompatible with the event declaration in the sensitivity list.

As we are checking the negedge of the RESET in the event list where the "q" is resettted for RESET =1, the condition got failed.

Is it the error due to target library components or logical error?????

 

[amraldo]

Re: a doubt in verilog

if u wrote something like this :

always @ (posedge clk or negedge reset)
  if (reset)
     q <= 0;
  ...

This means this always block is to be executed on positive edge clock & the reset is ??
from sensitivity lest it is active low but from ur condition it is active high so it is not synthesiable.
ur solution is correct.
Hint: Read The HDL manual of ur synthesizer before using it. you will find code examples for most of blocks u want to describe.
Regards,
Amraldo