hariharan4000
Junior Member level 1

hi
can any one clear me this problem related wth verilog?
for the folowing stmt
always@(posedge clk or negedge reset)
.
.
.
endmodule
// i am getting the code simulated correctely but NOT synthesisable..
when i change the stmt always@(posedge clk or posedge reset)
it gets synthesised
y i am not getting synthesised i mix rising and falling edge.?
what is the reason?
can any one clear me this problem related wth verilog?
for the folowing stmt
always@(posedge clk or negedge reset)
.
.
.
endmodule
// i am getting the code simulated correctely but NOT synthesisable..
when i change the stmt always@(posedge clk or posedge reset)
it gets synthesised
y i am not getting synthesised i mix rising and falling edge.?
what is the reason?