Why I can combine two EPM7128S projects?

[wwwrabbit]

Why not fit?

Hi, everyone,
I got a new question.
I have tow projects. using EPM7128S. one using 35% resource, another using 59% resource.
so I want to combine them togather. but it failed. can't fit in. seems weird.

If there is anyway to fit them in?
Changing language from verilog to AHDL, does it help?

 

[lucbra]

Re: Why not fit?

Hi wwwrabbit,

Fitting is usually quite straightforward. Look at the number of registers of both designs, the number of functions that you implement, add all together and you'll get an estimate if your combined design will fit.
Of course, if you're using wide functions, you're stealing resources from adjacent macrocells.
Usually, you can change settings from the fitter to better accomodate your needs.
Don't ask how to do it in MAX+, I'm not familiar with it. I'm using Lattice CPLDs. With their ispExplorer you can change some parameters influencing the fitting process, and you can really get the maximum out of it.
Also, the EPM7128S has not a very rich featureset, maybe changing to AHDL would help.

 

[r_e_m_y]

Re: Why not fit?

Hi wwwrabit,

what is the message delivered in the report file ?

I don't think that use AHDL will help you to fit your design.
You can try to modify the global project logic synthesis option (multi level synthesis for max7000 has already help me ...)

:wink:

 

[wwwrabbit]

Re: Why not fit?

I don't think AHDL will help too.
what bothers me is that project 1 use 50 LC(logic cell) and project 2 use 60 LC(logic cell). put them togather then it need 144 LCs.

I already checked the "multi level synthesis for max7000 " before I synthesis.

Thanks your guys.

 

[r_e_m_y]

Re: Why not fit?

hi wwwrabit,

how many Synthesized logic cells are required ?
how many Total logic cells required ?

are your 2 functions totally independant or do they interract together ?

:?: