When reading "The Art of Analog Layout (Sencond Edition)", it said that ESD protection is not needed in test pad and probe pad because the are encapsulated in package after assembling, but when testing the chip before assembling, whether the test pad and probe pad suffer ESD from probes? why ESD protection needn't in test pad and probe pad?
a test environment can be carefully controlled to avoid possible ESD hazards, by using well grounding of human boday and probe tips, there is no potential ESD risk, as long as those pads are not bond out to package level, they are safe.