Ahmed_Sawaf
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verilog-a initial keyword
Hi all,
This is my first time to expose to Verilog-A, anyone help me please by answering these simple questions (hopefully)
1) What is the mean of "descipline" and "nature" statements? where do I use?
2) What is it meant by the backquot character: (`) when it come before a word such that `include or `define or `BITS and so on?
3) What is the difference between the two approaches:
---Top-Down Design and:
---Buttom-Up Design (or verification?) ??
if anyone has some example of analog components writen in Verilog-A please upload it here..
Thank you very much...
Best Regards...
Hi all,
This is my first time to expose to Verilog-A, anyone help me please by answering these simple questions (hopefully)
1) What is the mean of "descipline" and "nature" statements? where do I use?
2) What is it meant by the backquot character: (`) when it come before a word such that `include or `define or `BITS and so on?
3) What is the difference between the two approaches:
---Top-Down Design and:
---Buttom-Up Design (or verification?) ??
if anyone has some example of analog components writen in Verilog-A please upload it here..
Thank you very much...
Best Regards...