modeling a PWL source in Verilog A

[cmos_ajay]

Hello, I would like to model a PWL source using Verilog A .
How can I do that ?

 

[dick_freebird]

Timing Statements — Documentation

Maybe the clues you need are to be found there, or attached
pages. verilogams.com appears to have absorbed (or be a
rebranding of) the old veriloga.com which had a pile o'
examples under it. All I have now are some stale html pages
archived.

Ken Kundert's designersguide.org is a separate, user based
veriloga resource.

 

[FvM]

$table_model should help.