Time-domain modeling of all digital PLL

[InvokeMeWell]

hello,
I am trying to write a matlab code in time domain for ADPLL, but my ADPLL never locks.
I have been searching all over the internet to find an example how to simulate an ADPLL, with no luck, has someone any reference or paper with an actual code or pseudo code how I can
lock an all DPLL.

My train of this for this is simple
for i = 1 :fref_cycles
fcw = ftarget/fref
fcw_int = int(fcw)
fcw_frac = fcw-fcw_int
the Rv pretty much is how many times rising edges of the DCO we have in on fref
the ε[k] = tdc_code(binary_output) * Tdco/tdc_res


the normalized dco I forget it, also the filter




end

 

[D.A.(Tony)Stewart]

https://web.engr.oregonstate.edu/~moon/research/files/cas2_mar_07_dpll.pdf

 

[kaz1]

View attachment 185781
hello,
I am trying to write a matlab code in time domain for ADPLL, but my ADPLL never locks.
I have been searching all over the internet to find an example how to simulate an ADPLL, with no luck, has someone any reference or paper with an actual code or pseudo code how I can
lock an all DPLL.

My train of this for this is simple
for i = 1 :fref_cycles
fcw = ftarget/fref
fcw_int = int(fcw)
fcw_frac = fcw-fcw_int
the Rv pretty much is how many times rising edges of the DCO we have in on fref
the ε[k] = tdc_code(binary_output) * Tdco/tdc_res


the normalized dco I forget it, also the filter




end

I suggest you generate ref and frequency then get error in a feedback loop to be added to Fo value below:

Fo = 12; %target frequency
Fs = 100; %sampling rate
ref = 12.01;

Fref = cos(2*pi*(0:999)*ref/Fs);
Fgen = cos(2*pi*(0:999)*Fo/Fs);

 

[InvokeMeWell]

https://web.engr.oregonstate.edu/~moon/research/files/cas2_mar_07_dpll.pdf

thanks for your reply and sorry for delayed answer, I am looking more on how to lock the ADPLL in time domain, e.g the DCO will start in frequency X but my target is Y freq, how vs time will lock I want. something like that in a plot :

this code exactly I am looking to create first, here is the output of the ADPLL vs time the target I presume is 1630 and shows the locking procedure.

 

[D.A.(Tony)Stewart]

Lock in Time has many variables. VCO gain. Filter gain-BW, phase margin (PM) initial/max error frequency. etc
There is a huge tradeoff for jitter and speed in number of cycles with the above variables.

I made a crude fast PLL that has poor PM and oscillates. Someone may improve. I don't have time now.

I provided a 100 kHz triangle sweep switch for VCO for testing.
Then 3 inputs 1 MHz, 1.46MHz, 2MHz with a 1P3T switch

Feel free to change any RC value then reset to see Lock time and residual phase error.

https://tinyurl.com/yotgcrba

 

[InvokeMeWell]

Lock in Time has many variables. VCO gain. Filter gain-BW, phase margin (PM) initial/max error frequency. etc
There is a huge tradeoff for jitter and speed in number of cycles with the above variables.

I made a crude fast PLL that has poor PM and oscillates. Someone may improve. I don't have time now.

I provided a 100 kHz triangle sweep switch for VCO for testing.
Then 3 inputs 1 MHz, 1.46MHz, 2MHz with a 1P3T switch

Feel free to change any RC value then reset to see Lock time and residual phase error.

https://tinyurl.com/yotgcrba

nice gui!! thanks foro sharing

 

[D.A.(Tony)Stewart]

Here's a filter variation of the integrator with a switch on pole and zero ( phase lead compensation)

https://tinyurl.com/yorzq97z

(Cap too big)

https://tinyurl.com/yuubxask corrected

https://tinyurl.com/yucxcumn clean up

--- Updated Nov 26, 2023 ---

Step 1. Find input frequency range and choose VCO to span this range with a little margin for error.
Step 2. Define max jitter % T
Step 3. Define lockup time in cycles.
Step 4 Design integration filter & phase compensation network for critical damping PM ~ 70 deg.
Step 5 Add Frequency Lock FL detect detector (no skip cycle) Add Phase Locked (PL) detector ( < jitter spec in x cycles),
Step 6 USE FL to control dual gain-bandwidth to satisfy 2&3 , fast lock, > low jitter.