How to find the time constant

[the_dumbwine]

Okay so I have a circuit, which I have attached given below.

Now I want to find the time constant of the circuit, considering there is equal caps placed at node X and Y.
The problem that I am facing is for small signal model i can easily find the time constant while the circuit is in small signal domain but since this is a latch circuit the feedback is positive so i assumed that all transistor get out of small signal domain and then it enters into large signal domain assuming all the transistors are in saturation, so i apply large signal model of mosfets in saturation but in this stage how should i find the time constant.

I would be a great help if you could provide me with a transfer function of (Vin1-Vin2)/(Vx-Vy) where the function is independent of Vy and Vx, because when I am solving, I am getting the dependence of Vx and Vx in the transfer function, so if someone knows how to solve it would be a great help.

 

[guntherleet]

Do you want to share your calculations?
Did you try to generate a small signal formulation for the M3&M4 structure?

 

[dick_freebird]

Since the load is not shown and neither are the gate drive levels
(or the transistor attributes, for that matter) I don't see how a
calculation is practical, let alone useful.

If you only want the form, not the value, I guess you could get there
with device capacitances, on and off currents etc. But in practical
design you would probably just pick library elements and start in
on tweaking W to get what you can, out of it.

 

[the_dumbwine]

Do you want to share your calculations?
Did you try to generate a small signal formulation for the M3&M4 structure?

I did the small signal formulation but it makes no sense in doing small signal afterall due to positive feedback large signal will kick in.

 

[the_dumbwine]

Since the load is not shown and neither are the gate drive levels
(or the transistor attributes, for that matter) I don't see how a
calculation is practical, let alone useful.

If you only want the form, not the value, I guess you could get there
with device capacitances, on and off currents etc. But in practical
design you would probably just pick library elements and start in
on tweaking W to get what you can, out of it.

Yes you are correct in practical design we tweak w and l but if i would be able to do through analysis of the circuit in each time frame i guess it would lead to better optimization thats why i am asking and you can consider c as load cap at both the ends of output. and rail voltage as vdd