Why do you all ignore me??! [ :( ] {Verilog-A Questions}

verilog-a initial keyword

Hi all,

This is my first time to expose to Verilog-A, anyone help me please by answering these simple questions (hopefully)

1) What is the mean of "descipline" and "nature" statements? where do I use?

2) What is it meant by the backquot character: (`) when it come before a word such that `include or `define or `BITS and so on?

3) What is the difference between the two approaches:
---Top-Down Design and:
---Buttom-Up Design (or verification?) ??

if anyone has some example of analog components writen in Verilog-A please upload it here..

Thank you very much...
Best Regards...

Verilog-A questions, plz continue help in this thread

1-descipline is a new property that u can create and calll anything
i.e. voltage is descipline and current is descipline but u can add ur own new desciplines like pressure or whatever(i never had to use them)
2-backquot is to indicate a keyword of the program like the ones u stated
3-the first is to do modeling then go in each block details (i.e. transistor level)
while the second is to start from each block in details (i.e. transistor level)

Re: Verilog-A questions, plz continue help in this thread

This is a usefull book..

Re: Verilog-A questions, plz continue help in this thread

Well, Thanks for helpful replies...

I have some other questions...

1. What is the @cross() function can do in digital block such as a flip-flop? does it have other similar functions? what are them? how to add a tolerance in both time and signal shape wahtever is it in the cross() function?? is the "@" operator reserved only for it or no?

2. what is the ::= operator? and the: expr1 : expr2 == expr3 mean?? for the last i know that its name is indirect branching, but what does that mean?! and what is it used in??

3. Can I generate a verilog-A code of certain know blocks using Cadence? I think if yes, that i need to adjust something in settings, as when i creat a new instance with tool selcted is: Verilog-A Editor, it just open the text editor with
`include() and module and end statements.. What i mean is to generate most known paramters and statements that describes something like a flip-flop or whatever...

4. what is the difference between the functions: idtmod() and idt() which should i use with a VCO module?

Thank you..waiting for feed back..
Regards,

Added after 42 minutes:

Sorry, another silly one..
Why do $strobe() and $display() function rather than other functions are prepended with the dollar sign "$" ?? what is the special thing that let them put it in them??

Thanks,

Ahmed_Sawaf said:

2) What is it meant by the backquot character: (`) when it come before a word such that `include or `define or `BITS and so on?

Click to expand...

The following compiler directives are available in Verilog-A. You can identify them by the initial
accent grave ( ` ) character, which is different from the single quote character ( ' ).

`define

`undef

`ifdef

`include

`resetall

`default_transition

Click to expand...

Quoted from page 170 Cadence Verilog-A Language Reference...
More details exists there..

Regards,
Ahmad,

I think the verilog-A manul can answer all ur questions.