Why do we need transition ATPG?

[swethapr565]

hi i would like to know why do we need transitional ATPG? can any let me to understand it well.

 

[maulin sheth]

Transitional ATPG is for detecting transition faults.(Gate delay or Path Delay faults).

 

[dftrtl]

What if by strcture the output of flop has huge capacitance. Stuck at will not catch it so we need to do transition faults

 

[swethapr565]

Thanks maulin & dftrtl. So my understanding in the requirement of transitional ATPG is as follows and correct me if i am wrong ... or need to understand more on it.
Nanometer technologies contain newer types of defects that are delay sensitive and can no longer be detected with traditional stuck-at tests. Today’s integrated circuits are seeing an escalating clock rate, shrinking dimensions, increasing chip density, etc. Consequently, there arises a class of defects that would affect the functionality of the design if the chip is run at a high speed. In other words, the design is functionally correct when it is operated at a slow clock. This type of defect is referred to as a delay defect.
High impedance shorts, resistive vias and bridges, in-line resistance, and crosstalk between signals are some of these types of defects that are commonly seen in today's nanometer designs. Since many of these defects cause faulty timing behavior rather than faulty logic behavior, they can be effectively caught only by applying the tests at system speeds. This has led to the required use of delay-based fault models in Automated Test Pattern Generators (ATPG) named Transition ATPG to target these defect types. Transition faults and path-delay are two delay-based fault models that are widely used today while performing at-speed testing.
Way to do transitional testing:
Testing for a delay fault requires applying a pair of test vectors in an at-speed fashion. This is used to generate a logic value transition at a signal line or at
the source of a path, and the circuit response to this transition is captured at the circuit’s operating frequency. The path-delay fault model considers the cumulative effect of the delays along a specific combinational path in the circuit. If the cumulative delay in a faulty circuit exceeds the clock period for the path, then the test pattern that can exercise this path will fail the chip. The segment delay fault model targets path segments instead of complete paths.

 

[dftrtl]

Your understanding is correct.